An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

Semiconductor integrated circuit device and a method of manufacturing the same

An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material

High-performance cmos soi device on hybrid crystal-oriented substrates

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

High performance stress-enhanced mosfets using si:c and sige epitaxial source/drain and method of manufacture

The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for stably obtaining an element structure of a shape/dimension as a design by reducing a difference of etching speeds of respective films, in a process for performing wetting processing on a face to which a plurality of the films are exposed by using a buffered hydrofluoric acid. SOLUTION: In the manufacturing method of the semiconductor device, element separation films 102 are formed on a silicon substrate 101 and silicon sacrifice oxide films 104 are grown in an element forming region. Impurities for forming a well and controlling a threshold of a transistor are implanted through the silicon sacrifice oxide films 104, and the silicon sacrifice oxide films 104 are removed by the buffered hydrofluoric acid. Ammonium fluoride in the buffered hydrofluoric acid is set to be not less than 20 wt. %, and the concentration of a hydrofluoric acid to be not less than 1 wt. %. COPYRIGHT: (C)2004,JPO&NCIPI

Suzuki Tatsuya

Papers

Method for manufacturing semiconductor device