Recent growth in the processing and memory resources of mobile devices has fueled research within the field of mobile virtualization. Mobile virtualization enables multiple persona on a single mobile device by hosting heterogeneous operating systems (OSs) concurrently. However, adding a virtualization layer to resource-constrained mobile devices with real-time requirements can lead to intolerable performance overheads. Hardware virtualization extensions that support efficient virtualization have been incorporated in recent mobile processors. Prior to hardware virtualization extensions, virtualization techniques that are enabled by performance prohibitive and resource consuming software were adopted for mobile devices. Moreover, mobile virtualization solutions lack standard procedures for device component sharing and interfacing between multiple OSSs. The objective of this article is to survey software- and hardware-based mobile virtualization techniques in light of the recent advancements fueled by the hardware support for mobile virtualization. Challenges and issues faced in virtualization of CPU, memory, I/O, interrupt, and network interfaces are highlighted. Moreover, various performance parameters are presented in a detailed comparative analysis to quantify the efficiency of mobile virtualization techniques and solutions.

A Survey of Mobile Device Virtualization: Taxonomy and State of the Art

Given any multiset F of points in the Euclidean plane and a set R of robots such that $$|R|=|F|$$
 , the Arbitrary Pattern Formation (APF) problem asks for a distributed algorithm that moves robots so as to reach a configuration similar to F. Similarity means that robots must be disposed as F regardless of translations, rotations, reflections, uniform scalings. Initially, each robot occupies a distinct position. When active, a robot operates in standard Look–Compute–Move cycles. Robots are asynchronous, oblivious, anonymous, silent and execute the same distributed algorithm. So far, the problem has been mainly addressed by assuming chirality, that is robots share a common left–right orientation. We are interested in removing such a restriction. While working on the subject, we faced several issues that required close attention. We deeply investigated how such difficulties were overcome in the literature, revealing that crucial arguments for the correctness proof of the existing algorithms have been neglected. The systematic lack of rigorous arguments with respect to necessary conditions required for providing correctness proofs deeply affects the validity as well as the relevance of strategies proposed in the literature. Here we design a new deterministic distributed algorithm that fully characterizes APF showing its equivalence with the well-known Leader Election problem in the asynchronous model without chirality. Our approach is characterized by the use of logical predicates in order to formally describe our algorithm as well as its correctness. In addition to the relevance of our achievements, our techniques might help in revising previous results. In fact, it comes out that well-established results like (Fujinaga et al. in SIAM J Comput 44(3):740–785, 2015), more recent approaches like (Bramas and Tixeuil, in: Proceedings of the 35th ACM SIGACT-SIGOPS symposium on principles of distributed computing (PODC), 2016; Bramas and Tixeuil, in: Proceedings of the 18th international symposium on stabilization, safety, and security of distributed systems (SSS), 2016) and ‘unofficial’ results like (Dieudonne et al., in: CoRR arXiv:0902.2851
 , 2009) revealed to be not correct.

Asynchronous Arbitrary Pattern Formation: the effects of a rigorous approach

https://hal-brgm.archives-ouvertes.fr/hal-01092325/document

On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms

A coarse-grained reconfigurable processing unit (RPU) consisting of $16 \times 16$ multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a $54~\hbox{mm} \times 31~\hbox{mm}$ die in TSMC 65 nm LP1P8M CMOS technology A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode $1920 \times 1080$ H264 video streams at 30 frames per second (fps) under 200 MHz REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a $143 \times $ improvement on energy efficiency The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor REMUS_LPP can decode $720 \times 480$ H264 video streams at 35fps with 245 mW under 75 MHz, achieving a 76% reduction in power dissipation and a $396 \times $ improvement on energy efficiency compared with the ADRES reconfigurable processor

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

State-of-the-art multiprocessor cache hierarchies propagate the use of a fixed granularity in the cache organization to the design of the coherence protocol. Unfortunately, the fixed granularity, generally chosen to match average spatial locality across a range of applications, not only results in wasted bandwidth to serve an individual thread's access needs, but also results in unnecessary coherence traffic for shared data. The additional bandwidth has a direct impact on both the scalability of parallel applications and overall energy consumption.In this paper, we present the design of Protozoa, a family of coherence protocols that eliminate unnecessary coherence traffic and match data movement to an application's spatial locality. Protozoa continues to maintain metadata at a conventional fixed cache line granularity while 1) supporting variable read and write caching granularity so that data transfer matches application spatial granularity, 2) invalidating at the granularity of the write miss request so that readers to disjoint data can co-exist with writers, and 3) potentially supporting multiple non-overlapping writers within the cache line, thereby avoiding the traditional ping-pong effect of both read-write and write-write false sharing. Our evaluation demonstrates that Protozoa consistently reduce miss rate and improve the fraction of transmitted data that is actually utilized.

https://www.cs.rochester.edu/u/sandhya/papers/isca13.pdf

Protozoa: adaptive granularity cache coherence

Power dissipation and energy consumption are becoming increasingly important architectural design constraints in different types of computers, from embedded systems to large-scale supercomputers. To continue the scaling of performance, it is essential that we build parallel processor chips that make the best use of exponentially increasing numbers of transistors within the power and energy budgets. Intel SCC is an appealing option for future many-core architectures. In this paper, we use various scalable applications to quantitatively compare and analyze the performance, power consumption and energy efficiency of different cutting-edge platforms that differ in architectural build. These platforms include the Intel Single-Chip Cloud Computer (SCC) many-core, the Intel Core i7 general-purpose multi-core, the Intel Atom low-power processor, and the Nvidia ION2 GPGPU. Our results show that the GPGPU has outstanding results in performance, power consumption and energy efficiency for many applications, but it requires significant programming effort and is not general enough to show the same level of efficiency for all the applications. The “light-weight” many-core presents an opportunity for better performance per watt over the “heavy-weight” multi-core, although the multi-core is still very effective for some sophisticated applications. In addition, the low-power processor is not necessarily energy-efficient, since the runtime delay effect can be greater than the power savings.

/pdf/comparing-the-power-and-performance-of-intel-s-scc-to-state-306aduwwxa.pdf

Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs

The problem of coordinating a set of autonomous, mobile robots for cooperatively performing a task has been studied extensively over the past decade. These studies assume a set of autonomous, anonymous, oblivious robots. A task for such robots is to form an arbitrary pattern in the two dimensional plane. This task is fundamental in the sense that if the robots can form any pattern, they can agree on their respective roles in a subsequent, coordinated action. Such tasks that a system of robots can perform depend strongly on their common agreement about their environment. In this paper, we attempt to provide a distributed algorithm for pattern formation in the case of no agreement on coordinate axes. We also discuss the limitations of our algorithm.

A distributed algorithm for pattern formation by autonomous robots, with no agreement on coordinate compass

General Purpose Graphics Computing Units can be effectively used for enhancing the performance of many contemporary scientific applications. However, programming GPUs using machine-specific notations like CUDA or OpenCL can be complex and time consuming. In addition, the resulting programs are typically fine-tuned for a particular target device. A promising alternative is to program in a conventional and machine-independent notation extended with directives and use compilers to generate GPU code automatically. These compilers enable portability and increase programmer productivity and, if effective, would not impose much penalty on performance.

/pdf/directive-based-compilers-for-gpus-2zmldzpwm0.pdf

Directive-Based Compilers for GPUs

This paper presents a deterministic algorithm for forming a given asymmetricpattern in nite time by a set of autonomous, homogeneous, oblivious mobilerobots under the CORDA model. The robots are represented as points on the2D plane. There is no explicit communication between the robots. The robotscoordinate among themselves by observing the positions of the other robots onthe plane. Initially all the robots are assumed to be stationary. The robotshave local coordinate systems de ned by Sense of Direction (SoD), orientationor chirality and scale. Initially the robots are in asymmetric con guration. Weshow that these robots can form any given asymmetric pattern in nite time.Keywords: Asynchronous, oblivious, mobile robots, pattern formation,chirality.1. IntroductionExecuting a collaborative task by a set of small, autonomous, mobile robots(also known as robot swarm [18]) has been a popular topic for the researchfor last few decades. The robots are assumed to be anonymous, homogeneous,oblivious and asynchronous. The robots together perform a complex job, e.g.,moving a big body [16], cleaning a big surface [13] etc. The individual unit orrobot in a system of swarm robots is less expensive than a big robot. Increasingor decreasing the number of robots in this system involves very simple hardwareor software modi cations and thus provides good scalability. Moreover, havingsimilar capability, if some robots fail, others can manage to execute the work.This feature makes the system to be more resilient to malfunction. In hostileenvironments, these robots are easily deployable to perform various complextasks cooperatively.

Swapnil Ghike

Papers

Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs

A distributed algorithm for pattern formation by autonomous robots, with no agreement on coordinate compass

Directive-Based Compilers for GPUs

Pattern Formation for Asynchronous Robots without Agreement in Chirality