This paper studies the performance of delay-constrained hybrid automatic repeat request (HARQ) protocols Particularly, we propose a fast HARQ protocol where, to increase the end-to-end throughput, some HARQ feedback signals and successive message decodings are omitted Considering quasi-static channels and a bursty communication model, we derive closed-form expressions for the message decoding probabilities as well as the throughput, the expected delay, and the error probability of the HARQ setups The analysis is based on the recent results on the achievable rates of finite-length codes and shows the effect of the codeword length on the system performance Moreover, we evaluate the effect of various parameters, such as imperfect channel estimation and hardware on the system performance As demonstrated, the proposed fast HARQ protocol reduces the packet transmission delay considerably compared with the state-of-the-art HARQ schemes For example, with typical message decoding delay profiles and a maximum of 2,…, 5 transmission rounds, the proposed fast HARQ protocol can improve the expected delay compared with standard HARQ by 27%, 42%, 52%, and 60%, respectively, independently of the code rate/fading model

Fast HARQ Over Finite Blocklength Codes: A Technique for Low-Latency Reliable Communication

Despite the evolution of cellular networks, spectrum scarcity and the lack of intelligent and autonomous capabilities remain a cause for concern. These problems have resulted in low network capacity, high signaling overhead, inefficient data forwarding, and low scalability, which are expected to persist as the stumbling blocks to deploy, support and scale next-generation applications, including smart city and virtual reality. Fifth-generation (5G) cellular networking, along with its salient operational characteristics—including the cognitive and cooperative capabilities, network virtualization, and traffic offload—can address these limitations to cater to future scenarios characterized by highly heterogeneous, ultra-dense, and highly variable environments. Cognitive radio (CR) and cognition cycle (CC) are key enabling technologies for 5G. CR enables nodes to explore and use underutilized licensed channels; while CC has been embedded in CR nodes to learn new knowledge and adapt to network dynamics. CR and CC have brought advantages to a cognition-inspired 5G cellular network, including addressing the spectrum scarcity problem, promoting interoperation among heterogeneous entities, and providing intelligence and autonomous capabilities to support 5G core operations, such as smart beamforming. In this paper, we present the attributes of 5G and existing state of the art focusing on how CR and CC have been adopted in 5G to provide spectral efficiency, energy efficiency, improved quality of service and experience, and cost efficiency. This main contribution of this paper is to complement recent work by focusing on the networking aspect of CR and CC applied to 5G due to the urgent need to investigate, as well as to further enhance, CR and CC as core mechanisms to support 5G. This paper is aspired to establish a foundation and to spark new research interest in this topic. Open research opportunities and platform implementation are also presented to stimulate new research initiatives in this exciting area.

Cognition-Inspired 5G Cellular Networks: A Review and the Road Ahead

This paper studies the performance of delay-constrained hybrid automatic repeat request HARQ protocols. Particularly, we propose a fast HARQ protocol where, to increase the end-to-end throughput, some HARQ feedback signals and successive message decodings are omitted. Considering quasi-static channels and a bursty communication model, we derive closed-form expressions for the message decoding probabilities as well as the throughput, the expected delay and the error probability of the HARQ setups. The analysis is based on recent results on the achievable rates of finite-length codes and shows the effect of the codeword length on the system performance. Moreover, we evaluate the effect of various parameters such as imperfect channel estimation and hardware on the system performance. As demonstrated, the proposed fast HARQ protocol reduces the packet transmission delay considerably, compared to state-of-the-art HARQ schemes. For example, with typical message decoding delay profiles and a maximum of 2,...,5 transmission rounds, the proposed fast HARQ protocol can improve the expected delay, compared to standard HARQ, by 27, 42, 52 and 60%, respectively, independently of the code rate/fading model.

Fast HARQ over Finite Blocklength Codes: A Technique for Low-Latency Reliable Communication.

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

Future railway is expected to accommodate both train operation services and passenger broadband services. The millimeter wave (mmWave) communication is a promising technology in providing multi-gigabit data rates to onboard users. However, mmWave communications suffer from severe propagation attenuation and vulnerability to blockage, which can be very challenging in high-speed railway (HSR) scenarios. In this paper, we investigate efficient hybrid beamforming (HBF) design for train-to-ground communications. First, we develop a two-stage HBF algorithm in blockage-free scenarios. In the first stage, the minimum mean square error method is adopted for optimal hybrid beamformer design with low complexity and fast convergence; in the second stage, the orthogonal matching pursuit method is utilized to approximately recover the analog and digital beamformers. Second, in blocked scenarios, we design an anti-blockage scheme by adaptively invoking the proposed HBF algorithm, which can efficiently deal with random blockages. Extensive simulation results are presented to show the sum rate performance of the proposed algorithms under various configurations, including transmission power, velocity of the train, blockage probability, etc. It is demonstrated that the proposed anti-blockage algorithm can improve the effective rate by 20% in severely-blocked scenarios while maintaining low outage probability.

Efficient Hybrid Beamforming with Anti-Blockage Design for High-Speed Railway Communications

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a binary Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioning the PCM into not only layers but superlayers we derive an upper bound on the two-layer pipelining depth for the compact representation. To validate the architecture, a decoder for the IEEE 802.11n (2012) QC-LDPC is implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler available in the NI LabVIEW Communication System Design Suite (CSDS). It offers an automated and systematic compilation flow where an optimized hardware implementation from the LDPC algorithm was generated, achieving an overall throughput of 608Mb/s (at 260MHz). As per our knowledge this is the fastest implementation of the IEEE 802.11n QC-LDPC decoder using an algorithmic compiler.

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture. While providing an algorithmic method to enhance parallel processing within the decoder in the first approach, in the second approach we apply the decoder architecture to achieve another highly-parallel architecture. We have successfully validated the second approach to get a 2.48Gb/s QC-LDPC decoder implementation operating at 200MHz on the Xilinx Kintex-7 FPGA in the NI USRP-2953R. For rapid-prototyping our research findings, the high-level description of the entire decoder was translated to a Hardware Description Language (HDL), namely VHDL, using the algorithmic compiler in the National Instruments LabVIEW™ Communication System Design Suite (CSDS™). As per our knowledge, at the time of writing this paper, this is the fastest FPGA-based implementation of a standard compliant QC-LDPC decoder on a USRP using an algorithmic compiler.

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

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FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Many varied domain experts use Lab VIEW as a graphical system design tool to implement DSP algorithms on myriad target architectures. In this paper, we introduce the latest LabVIEW FPGA compiler that enables domain experts with minimum hardware knowledge to quickly implement, deploy, and verify their domain-specific applications on FPGA hardware. We present two compiler techniques that we use to 1) extract extra parallelism from a user's application to take advantage of the parallel hardware resources of the FPGA and 2) minimize memory-access traffic, which is often a bottleneck that restricts overall FPGA performance. Finally, our approach provides the user a simple constraint-driven experience to maximize their development efficiency. We use two case studies in two different domains, a 3GPP Turbo decoder and a Smith-Waterman algorithm, to show the benefits our tool provides to users.

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA

In this paper, we present families of rate compatible (RC) structured irregular repeat-accumulate (SIRA) and structured generalized irregular repeat-accumulate (SG-IRA) codes, which are particularly attractive for 5G wireless systems due to their linear-time encoding property. The family of codes is generated using a technique called row-splitting, in which a high-rate G-IRA code is designed as a mother code and lower-rate codes are generated from the mother code by splitting the rows of the systematic part of the parity-check matrix. We propose this technique as a way to support a variety of code rates for an Incremental Redundancy (IR) based hybrid ARQ (HARQ) scheme also known as Type-II HARQ for 5G millimeter wave wireless systems.

Swapnil Mhaske

Papers

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA

Rate compatible IRA codes using row splitting for 5G wireless