In the fast moving digital world, it becomes imperative to constantly come up with innovation in digitization. The analog to digital converter is the second most widely used device in the world of electronic circuits. ADCs are composed of dynamic comparators. To overcome the challenges faced due to the digital change, improved versions of the conventional comparator design for high-speed functioning and low power consumption has been proposed. Area is another main factor when keeping in mind the design of these dynamic comparators. 180 nm CMOS technology and a constant supply voltage of 0.8V have been used. A conventional double tail comparator has been designed by adding transistors without hindering the functionality. This provides faster, more efficient modification of the comparator design. A new design for a dynamic regenerative double-tail comparator has been proposed which uses clock-gating techniques. This further reduces the power consumption and provides higher speed by reducing the delay time of the circuit.

Design of a low power, high speed double tail comparator

Comparator is fundamental building blocks in analog-todigital converters. CMOS comparator which has dual input, dual output inverter stage suitable for high speed analog-to-digital such as flash pipeline ADCs it require high-speed with small chip area low voltage and low power. In this paper a double tail comparator by using clock gating technique is designed in such a way to reduces the overall propagation delay by replacing a existing comparator with a proposed double tail dynamic comparator it reduces the power and voltage by increasing the speed. Without changing the design modified method replace some pair of transistors connected in parallel for proposed comparator due to mismatch in transistor pairs. The design is simulated by using Tanner EDA Tools. The supply voltage (1.2 V) while consuming 9μW in modified comparator. It is shown that in the modified comparator both the power consumption delay time are reduced.

Design of Low Power Area Efficient Double Tail Comparator

In analog and digital converters are tragedies dynamic parts during creation of voltaic structures. This paper, a 0.7-V, 3-bit CMOS flash analog to digital converter is presented at 45-nm technology. The major constituents of ADC are comparators and thermometric code to binary code (TC to BC) encoder. Comparator is the key mechanism mainly used in analog to digital converters (ADCs). For the improved transmission of signals, necessities of best analog to digital converters are requisite. Flash ADCs are valuable module in signal processing and communication system. In digital domain low power and low voltage become a extensive component in that are difficult for designing high speed devices and converters. As require for mixed integrated circuits increase, the design of analog circuits such as operational amplifiers in CMOS technology become more important. The power dissipation for flash ADC is 218.9-μW. This established in the recommended method be able to reduce power consumption equated with the predictable single. In this paper, power consumption of the comparators has reduced, in the mainly vital structure of such ADCs. The power consumption of comparator is 26.72-μW.

An effective 3-bit Flash Analog to Digital Converter using 45-nm Technology

In the present works, mainly power consumption of circuit is main issue for every designers. This paper mainly dealing with the implementation of CMOS Charge sharing latch Comparator and analysis of it using different parameter in 90nm.For the implementation of new design the features of two important Comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two Comparator are Resistive Dividing Comparator and Differential Current sensing respectively. The simulation result is shown in 90nm technologies, for 2.4GHz clocked comparator by using 0.9V input. Again the result of 90nm technology is compared with 180nm technology to show the reduction of power and enhancement of speed. The implementation is done on the Cadence virtuoso design environment. Keyword: Power analysis, CMOS latch comparators.

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Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

This paper present a new design of comparator for flash ADC . The flash ADC is the fastest Application ADC that requires the high speed comparator. The new design consist of sense amplifier and SR Latch ,the combining configuration of design have the considerable stable output which helps in high speed and resolution. The use of SR symmetric latch makes stable output as compared to the conventional SR latch moreover the design has high resolution. This paper has been done in 180 nm and 90nm gpdk in CADENCE VIRTUOSO. For low power application. There are many issues in the design of the comparator, we will discuss those design issues in this paper. I. Introduction The design of comparator is the most critical part in the flash ADC, since the speed and the resolution is determined by the comparator. The dual tail current sense amplifier based comparator can run faster with lower supply voltage than the normal one, and the kick back effect is also better than the normal one. The symmetric S-R latch provides shorter delay time and stable time than the normal S-R latch. Combing the sense amplifier based comparator and the symmetric S-R latch, the whole block can run faster and the output signal is more stable than the normal structure. This design of comparator is for 2GSample/sec flash ADC. Based on IEEE 802.15.3a WPAN UWB applications, the signals using multi-band orthogonal frequency division multiplexing (MB-OFDM) occupy a bandwidth of 528MHz for every band. It requires the conversion rate at least higher than 1.06GSample/sec. 1.1. The Analysis Of The Traditional Sense Amplifier Based Comparator And Sr Latch: In the analysis of any comparator there are 2 stages in which operation is divided, one is reset phase and other is regeneration phase. In this sense amplifier based comparator sense amplifier connects positive feedback with the resistive input as shown in fig.1.Now during reset phase when clock is low, the nodes of inverters (M1-M4) are charged to Vdd, through transistor M7 and M8. Again on regeneration phase when clock is high Nmos transistor M9 is turned on which is a part of differential pair M5 and M6. Current flowing through this pair controls the latch circuit and small changes between differential pair cause large output change. And this differential pair discharge the node Ni, and later difference of the input voltage will built charge it. When Ni come to Vth voltage then inverter M1,M3 turns on and this wil start the positive feedback. After Ni comes to 2Vth below Vdd transistor M2,M4 are turn on. Now with the help of strong positive feedback small input converted to full differential output. For the generation of output there is very short period of time in sense amplifier when its gain is good.so switch M11 ,M12 is added to increase the integration time. In the conventional sense amplifier, it is better to add a reset switch (M11, M12) connecting the Vdd and the Di so as to increase the integration time . In the sense amplifier there is only a very short time in which the differential pair actually have the gain. Actually the differential pair comes to triode region during Ni drop to Vth. This reset transistor also increase the active time of differential pair and decrease the offset effect in coming signals.

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Sweta Sahu

Papers

Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

Performance analysis of High Speed ADC using SR F/F