We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, fine-granularity elasticity can be introduced at the level of functional units (e.g. ALUs, memories). A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented. The opportunities this protocol opens for microarchitectural design are discussed.

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Synthesis of synchronous elastic architectures

The construction of formal models of real-time distributed systems is a considerable practical challenge. We propose and illustrate a pragmatic incremental approach in which detail is progressively added to abstract system-level specifications of functional and timing properties via intermediate models that express system architecture, concurrency and timing behaviour. The approach is illustrated by developing a new formal model of the cardiac pacemaker system proposed as a "grand challenge" problem in 2007. The models are expressed using the Vienna Development Method (VDM) and are validated primarily by scenario-based tests, including the analysis of timed traces. We argue that the insight gained using this staged modelling approach will be valuable in the subsequent development of implementations, and in detecting potential bottlenecks within suggested implementation architectures.

/pdf/incremental-development-of-a-distributed-real-time-model-of-kmvz46qhni.pdf

Incremental Development of a Distributed Real-Time Model of a Cardiac Pacing System Using VDM

Incremental Development of a Distributed Real-Time Model of a Cardiac Pacing System using VDM

We formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove fundamental compositionality results. The paper contributes to bridging the gap between the theory of latency-insensitive systems and the correct implementation of efficient control structures for them

/pdf/synchronous-elastic-networks-1m4p1pyz8a.pdf

Synchronous Elastic Networks

We present an agile formal methodology named eXtreme Formal Modeling (XFM), based on Extreme Programming (XP) concepts to construct abstract models from natural language specifications of complex systems. In particular, we focus on Prescriptive Formal Models (PFMs) that capture the specification of the system under design in a mathematically precise manner. Such models can be used as golden reference models for formal verification, test generation, coverage monitor generation, etc. This methodology for incrementally building PFMs works by adding user stories expressed as LTL formulae gleaned from the natural language specifications, one by one, into the model. XFM builds the models, retaining correctness with respect to incrementally added properties by regressively model-checking all the LTL properties captured theretofore in the model. We illustrate XFM with a graded set of examples consisting of a traffic light controller and a DLX pipeline. To make the regressive model-checking steps feasible with current model-checking tools, we need to control the model size increments at each subsequent step in the process. We therefore analyze the effects of ordering the LTL properties in XFM on the statespace growth rate of the model. We compare three different property-ordering methodologies: ad hoc ordering, property-based ordering, and predicate-based ordering. We experiment on the models of the ISA bus monitor and the arbitration phase of the Pentium Pro bus. We experimentally show and mathematically reason that the predicate-based ordering is the best among these orderings. Finally, we present a GUI-based toolbox that we implemented to build PFMs using XFM.

/pdf/xfm-an-incremental-methodology-for-developing-formal-models-13vo00jzj8.pdf

XFM: An incremental methodology for developing formal models

http://pop-art.inrialpes.fr/~girault/Fmgals07/Final/05-suhaib.pdf

Dataflow Architectures for GALS

With increasing clock frequencies, the signal delay on some interconnects in a system on chip (SoC) often exceeds the clock period, which necessitates latency insensitive protocols (LIPs). The correctness of a system composed of synchronous blocks communicating via LIPs is established by showing latency equivalence between a completely synchronous composition of the blocks, and the LIP-based composition. Every time a new LIP is conceived, it needs to be debugged and then proven correct. Mathematical theorems to establish correctness, though elegant, are error prone, and tedious to create for every new variant of LIPs. In this work, we present validation frameworks for families of LIPs, both for dynamic validation, useful for early debug cycles, and formal verification for formal proof of correctness. This can be a useful framework in the hands of designers trying to create new LIPs or to optimize existing ones for design convergence

/pdf/validating-families-of-latency-insensitive-protocols-1tisnzk4uf.pdf

Validating families of latency insensitive protocols

In this paper, we show the usefulness of an agile formal method (named XFM) based on extreme programming concepts to construct abstract models from a natural language specification of a complex system Building formal models for verification purposes is being employed in the industry for two different usage modes: (i) descriptive formal models (DFM) which, are used to capture an implementation into an abstract model to submit to analysis by model checking tools, (ii) prescriptive formal models (PFM) which, are used to capture natural language specifications into a formal model to analyze consistency of the specification and also as a reference model to compare a DFM against it We propose XFM as a methodology to incrementally build a correct PFM from a natural language specification In this paper, using XFM, on various examples related to microprocessors, we build the models of DLX pipeline in SPIN, the ISA bus monitor and arbitration phase of the Pentium Pro bus in SMV

/pdf/extreme-formal-modeling-xfm-for-hardware-models-4eiobgt4pw.pdf

Extreme formal modeling (XFM) for hardware models

With increasing clock frequencies in the gigahertz ranges, the distance signals travel during one clock cycle decreases, making a synchronous clock routing throughout the chip impossible. Therefore, interconnect latency needs to be tolerated, and in IP based design various synchronous logic blocks need to be connected via long interconnects that have communication delays of multiple clock cycles. Sometimes two communicating IPs also belong to different clock domains, making their interaction difficult to implement. Latency insensitive protocols were introduced for cases when the interconnect delay was the main concern but the IPs were under same clock domain. Here we generalize the issue of solving the problem of long interconnects in between IPs for a single-clock domain as well as for a multi-clock domain. We also use a formal verification strategy for making sure that as we gradually refine our protocol, we do not become functionally inequivalent to the original synchronous reference design. Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design Syed Suhaib, David Berner, Deepak Mathaikutty, Jean-Pierre Talpin, Sandeep Shukla {ssuhaib,damathai,shukla}@vt.edu {david.berner,talpin}@irisa.fr Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design Syed Suhaib, David Berner, Deepak Mathaikutty, Jean-Pierre Talpin, Sandeep Kumar Shukla Virgina Tech, USA INRIA, France {ssuhaib,damathai,shukla}@vt.edu {dberner,talpin}@irisa.fr

/pdf/presentation-and-formal-verification-of-a-family-of-2qszt8k1rq.pdf

Syed Suhaib

Papers

XFM: An incremental methodology for developing formal models

Dataflow Architectures for GALS

Validating families of latency insensitive protocols

Extreme formal modeling (XFM) for hardware models

Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design