A new sinusoidal oscillator using Carbon Nanotube Field Effect Transistors (CNTFET) based Operational Transconductance Amplifiers (CNOTA) with grounded capacitors is presented in this paper. The proposed current-mode oscillator thus implemented and having grounded capacitor feature, fulfils the need for realizations of systems used in combination with various other systems/ subsystems - both voltage-mode and current mode. It also ensures simplicity in implementation by using a single-ended CNOTA. The analytical model is given for the circuit leading to fulfilment of the condition of oscillation at tuned frequency. The proposed sinusoidal oscillator is primarily used in the field of signal dispensation applications, telecommunication networks, communication-equipment and control modules. The benefits derived from the introduced model are validated by simulation carried out at a supply voltage of \pm 1.8V in Cadence virtuoso using spectre model libraries. They are further tested with the aid of 32 nm model of Carbon Nanotube Field Effect Transistor (CNTFET) technology obtained through open source. The proposed design (and the model provided) is found to be in good agreement with the obtained results.

/pdf/an-operational-transconductance-amplifiers-based-sinusoidal-q4e26os4b9.pdf

An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

A robust square wave generator employing a sole capacitor and two resistors has been presented in this study. Low power as well as popular translinear circuit scheme of Second generation current controlled current conveyor-CCCII has been taken as an active element to implement the proposed square wave generator. CCCII inhibits promising features like availability of three mutually independently and electronically adjustable parameters corresponding transconductance (gm), intrinsic resistance (r) of the current input terminal and current gain between two terminals) that are very prevalent for control applications accepted currently. The operating frequency of the proposed model has been analyzed with respect to the passive components present there, with no exposure of output signals to the thermal voltage (VT). Electrical/Device properties (like Noise, Threshold, area etc.) of the proposed circuit have also been discussed in this work. The simulation work was carried out on Synopsis Hspice tool (v-2008.03) from Avant. Satisfying results with anticipation of theoretical and simulated results, including precision (consistency assessment) with Pareto analysis (Ist order Best Test flavored by Decision making analysis) were observed during the study. The 45 nm BSIM CMOS modelling parameters were adopted to prove the theory. The elementary purpose of using such parameters is to maximize the circuit drive and lowering the leakage current. Another purpose of using these modelling parameters is to enhance the realization of the proposed circuit in the form of chip die and further get it fabricated in custom Integrated circuit(IC) form, from a Standard local foundry. Maximum power consumption of the circuit is 600 µW, with ± 1 V rail to rail operating voltages.

/pdf/a-novel-square-wave-generator-based-on-the-translinear-4s1rmmhpyy.pdf

A novel square wave generator based on the translinear circuit scheme of second generation current controlled current conveyor-CCCII

The paper presents a new all pass filter using Voltage Difference Transconductance Amplifier (VDTA). It operates in voltage mode. The circuit that has been proposed comprises of two VDTA's, two capacitors without using resistor. The devised circuit uses a bias current of order 150 μA, operates at a supply voltage of ±0.9 V and its amplitude is electronically controllable/tunable with the bias current. The circuit is implemented in a generic process design kit 180 nm CMOS technology using a Cadence Virtuoso tool.

A Voltage Mode All Pass Filter Employing Voltage Difference Transconductance Amplifier

Schmitt trigger is designed using the single second generation Current Controlled Conveyor. The proposed configuration utilizes single CCCII and only two externally connected resistors and is able to produce dual output square wave signal. The topology has the benefit of having a simple circuit, offering a large bandwidth and improved slew rate. PSPICE simulator using OrCad 16.3 version, 0.35 µm CMOS technology is used to verify the design, hysteresis is determined and compared with the existing methods available in the literature. The proposed configuration is tested using the experimental setup involving CFOA (AD844AN) and OTA (LM13700). The results have been found satisfactory in both simulation and experimental aspect. Montecarlo analysis and worstcase analysis are determined to prove the circuit efficiency in terms of critical parameters such as resistance with a tolerance of 5%. The hysteresis is also determined, that can reduce the effect of noise, able to produce exact square wave at the output. Schmitt trigger circuits find the applications in the field of Biomedical applications, analog signal processing, communication systems, waveform generators, pulse width modulators, multivibrators, flip-flops and in many other amplifier circuits. The basic application of Schmitt trigger is a square wave generator. The proposed topology is the best suited for monolithic IC fabrication.

/pdf/a-novel-dual-output-schmitt-trigger-using-second-generation-1x6l50xnq5.pdf

A Novel Dual Output Schmitt Trigger Using Second Generation Current Controlled Conveyor

Residue Number System (RNS) has the specific feature to perform addition, subtraction independently with carry-free propagation In RNS, conversion is of two types: Forward Conversion and Reverse Conversion Chinese Remainder Theorem (CRT) and Mixed Radix Conversion (MRC) are the two extensively used techniques adapted for reverse conversion and in this case, CRT is proved faster than MRC This paper proposes a residue to binary reverse converter for three moduli set {2n+ 1, 2n, 2n- 1} by modifying the CRT It is simplified in order to design a reverse converter that does not require modular operations The operations required in the existing designs are mod (2n) mod (2n – 1) and mod (2n – 1) operations The proposed design provides better results in terms of power, area, delay and number of cells over the existing CRT design and does not require mod operations which are however necessary in the existing CRT technique This design has been simulated using NC Launch - Encounter tool in Cadence

Analysis and Design of High Speed Residue to Binary Reverse Converter for the Moduli Set {2n+ 1, 2n,2n-1}

The immense work presented in this paper is a high frequency sinusoidal oscillator using positive second generation current controlled conveyor (CCCII+) with minimum passive components. CCCII is implemented using single Current Feedback Operational Amplifier (CFOA) and single Operational Trans-conductance Amplifier (OTA). The frequency (time period) of CCCII is tuned to a maximum of 4 MHz using external bias current. The performance of the proposed circuit is practically verified using ICs AD844 (CFOA) and LM 13700 (OTA) and its results are included. The topology is suitable for monolithic IC fabrication.

http://ieeexplore.ieee.org/iel7/7469254/7475237/07475323.pdf

A high frequency tunable sinusoidal oscillator using single CCCII

A Simple Schmitt Trigger Using SecondGeneration Current Controlled Conveyor

A current mode multiplier is a valid structured block in many signal processing operations, such as modulation and demodulation schemes in communications, in development of bio-medical equipments, in analog computations, and fuzzy logic controllers. A single second generation current controlled conveyor (CCCII) based current mode multiplier without passive components is designed. CCCII has the eccentricity of intrinsic resistance in between the two input ports which are tunable by the external bias current. PSPICE simulator is utilized to examine the proposed design. The topology yields a simple structure and highly suitable for monolithic IC fabrication. Simulation results are confirmed with a voltage requirement of ± 2.5 V, the non linearities, total harmonic distortion (THD), and power dissipation are anticipated. Comparison of the proposed design with the existing methods is also performed. The parametric sweep and temperature analysis are also determined. The simulated results very well agree with the theoretical expectancy.

A New Current Mode Multiplier Using Single CCCII Without Passive Components

This paper demonstrate a new design technique for the implementation of sub-threshold voltage range domino logic gates using MOSFETs. The paper shows the implementation of the sub-threshold voltage domino logic for OR, and AND gates. These circuits work in the sub-threshold voltage range, hence, drastically reducing power consumption. This is achieved by adding a voltage boosting block that is introduced with the value of a capacitor of 1 pF which creates a faster and power-efficient pull-down network. These proposed circuits are operated at sub-threshold voltages. These circuits are simulated with +0.3 V supply voltage to yield results with good driving capability and good noise margins. The proposed circuits are designed using gpdk 180 nm CMOS design process using an LTspice tool.

Syed Zahiruddin

Papers

A high frequency tunable sinusoidal oscillator using single CCCII

A Novel Dual Output Schmitt Trigger Using Second Generation Current Controlled Conveyor

A Simple Schmitt Trigger Using SecondGeneration Current Controlled Conveyor

A New Current Mode Multiplier Using Single CCCII Without Passive Components

Sub-Threshold Voltage Operated High Speed Domino Logic OR and AND Gates