In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints.

Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations

The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed.

Fourier Transform Computers Using CORDIC Iterations

A modified fast Fourier transform algorithm is described together with a real-time pipelined implementation. The approach is particularly suited to sequentially presented input data. The method can be used for both mixed and uniform radix number implementations. For example, for the radix-4 implementation, the method requires less data memory and only 1/3 of the number of complex multipliers of a conventional design. >

A pipelined FFT processor for word-sequential data

The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

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Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-/spl mu/m BiCMOS technology. The core area of this chip is 6.8 mm/sup 2/. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.

/pdf/a-64-point-fourier-transform-chip-for-high-speed-wireless-mlvj6hcguu.pdf

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

The fast Fourier transform algorithm is derived by means of successive fracturing of one-dimensional data strings into two-dimensional arrays. Using this formulation, a diagrammatic representation of mixed radix and highest radix FFT algorithms is derived. Using this representation, two broad classes of FFT hard-ware are explored, from the point of view of speed, parallelism, radix number, and type of memory.

Parallelism in fast Fourier transform hardware

The speed of present-day logic elements is such that it is possible to effect real-time spectrum analysis of audio frequency signals by means of digital hardware. This paper describes a structure that computes the discrete Fourier transform of a 400-point time sequence in 10 ms. This allows the real-time analysis of signals having components in the range from dc to 5 kHz. A high-speed bipolar arithmetic section is used in conjunction with relatively slower MOS shift registers and READ-ONLY memory to provide an efficient and economical design.

T. Bially

Papers

Parallelism in fast Fourier transform hardware

Audio frequency spectrum analysis using MOS memory elements