The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

We present a new routing region definition and ordering (RRDO) scheme for building block layout. Given an arbitrary placement of rectangular blocks (including the case with cycles in the channel precedence constraints), without modifying the placement, our scheme defines and orders channels so that when a new channel is being routed, its width can be expanded or contracted without destroying the previously routed channels. The cycles in the channel precedence constraints are broken by introducing a new kind of channel--the L-shaped channels. Unlike switchboxes, L-shaped channels can be expanded or contracted to permit the completion of routing without rerouting other existing channels. An efficient greedy RRDO algorithm has been implemented, which tries to generate as few L-shaped channels as possible since L-shaped channels are harder to route than straight channels. Our algorithm represents routing regions by a floor plan graph, for which we provide a precise definition and a construction algorithm. The experimental results of the RRDO algorithm are promising.

Routing Region Definition and Ordering Scheme for Building-Block Layout

In the traditional approach to channel routing, terminals must be located on grid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Terminals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C language, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

Glitter: A Gridless Variable-Width Channel Router

In the traditional approach to channel routing, terminals must be located ogrid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Termi­ nals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C lan­ guage, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

Glitter: A Gridless V ariable- Width Channel Router

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 /spl mu/m, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation. >

Routing in a three-dimensional chip

An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown.

T. Chiba

Papers

An Automatic Routing Scheme for General Cell LSI