A computer implemented process for detecting errors in a computer system including the steps of executing sequences of instructions of a software program (12) on each of a reference system (16) and a test system (15), detecting and recording state of the reference system (16) and the test system (15) at comparable points in the execution of the program (12), and comparing the detected state of the reference system (16) and the test system (15) at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system (16) and the test system (15) is automatically replayed if a difference in the compared state of the systems is detected.

Method and apparatus for correcting errors in computer systems

On the "Happa" parallel microcomputer system, faults were experimentally examined for the boundary of its operating range. Global bus faults, torus communication faults, and others were observed. A backup RAM technique is proposed for bus faults. >

Experiments of faults on the "Happa" system and a proposal of backup RAM technique

The architecture and implementation of an application-specific processor, the G100FTS, designed for fault-tolerant systems are described. The G100FTS integrates the core processor and the support module for fault-tolerant operation. The core processor is the 32-b microprocessor Gmicro/100 based on the TRON specifications. The support module provides a mechanism of error detection, a rollback operation that recovers a processor from a transient fault, diagnosis of faulty processors, and reconfiguration of a single processor system to make it operate continuously. The G100FTS drastically reduces the component count of a system and provides high system reliability. The G100FTS performs all the fault-tolerant operations in hardware and requires no dedicated programs for fault tolerance. The chip contains 805K transistors within a chip size of 13 mm /spl times/ 14 mm. A 1.0-/spl mu/m, double-metal CMOS technology was used.

T. Enomoto

Papers

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems