The utility of microelectronic devices and the yield of a microelectronic fabricating process is increased by providing, in addition to the desired circuits, "redundant" circuits of the same type. Each circuit has included, in at least one access lead, a nonvolatile, electrically alterable semiconductor device, which can be "set" to either conduct or not conduct power to the circuit. During testing, only the desired number of devices are rendered accessible by "setting" the semiconductor device to conduct. A microelectronic device having repetitive rows and/or columns for memory cells or logical processors is provided with additional rows and columns. An electrically alterable device is placed in each row and column. Upon the successful test of each row, the row enabling device is set to a conductive state. Any row containing a defective device is not enabled. If additional defects exist, and no redundant rows are available, redundant columns are disabled to isolate the defective devices.

Method for providing reconfigurable microelectronic circuit devices and products produced thereby

An electrically programmable logic array (10) for binary signals having signal inputs (A₀-Ax) and signal outputs (Q₀-Qi) comprises two row lines (a₀,a0'- ax, ax') for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q₀-qi) is provided. In the non-programmed state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S₀,S0',- Sx, Sx') which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

Electrically programmable logic array

A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Dual-addressed rectifier storage device

A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save space on the chip by employing a virtual ground feature and to operate fast due to a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line and to an output line, using a minimum number of transistors. The Y lines are precharged to a value significantly less than the chip supply voltage, so that operating speed is enhanced.

Virtual ground read-only-memory for electronic calculator or digital processor

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Semiconductor storage device

An integrated circuit read only memory fabricated on a single semiconductor chip, the memory cell array being arranged with orthogonal sets of access lines providing coincident selection of unidirectional current devices, for example, base-emitter diodes, at the junctions of the access lines. The memory cells are read by detecting the presence or absence of current flow through one or more selected cells. One set of access lines is formed by base diffusion stripes spaced apart in a common-collector isolation well. The orthogonal set of access lines is formed by metal lines overlying the base stripes and the individual emitters diffused in the base stripes at the points of intersection with the metal lines. Programming of the bit pattern is accomplished by contacts between the emitters and the metal lines at selected cross-over points. An improved inverter circuit is provided in the memory array access circuitry.

T Hornak

Papers

Integrated circuit read only memory bit organized in coincident select structure