This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V DD and threshold voltage V TH in active and standby modes. In the active mode, on the basis of delay monitoring results, either V DD control or V TH control is selected to avoid any oscillation problem between them. In V DD control, on the basis of delay monitoring results, V DD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V TH control, on the basis of power monitoring results, V TH is adjusted so as to maintain a certain switching current I SW /leakage current I LEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I SUBTH to substrate current I SUB ) is improved by taking into consideration both the effects of lowering V DD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I SW /I LEAK ratio in the active mode and 2) detect optimum body bias conditions (I SUBTH = I SUB ) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique. SVL technique is leakage current reduction technique. Simulation is done by using a microwind 3.1 and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.

Used self-controllable voltage level technique to reduce leakage current in DRAM 4×4 in VLSI

The demand for power sensitive designs in system-on-chip (SoC) has grown significantly as MOSFET transistors scale down. Since portable battery powered devices such as cell phones, PDA’s, and portable computers are becoming more complex and prevalent, the demand for increased battery life will require designers to seek out new technologies and circuit techniques to maintain high performance and long operational lifetimes. As process dimensions shrink further toward nanometer technology, traditional methods of dynamic power reduction are becoming less effective due to the increased impact of standby power. Therefore, this paper proposes a novel adaptive power management system for nanoscale SoC design that reduces standby power dissipation. The proposed design method reduces the leakage power at least by 500 times for ISCAS’85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

Adaptive Power Management for Nanoscale SoC Design

As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.

T.K. Pavan

Papers

Implementation of delay and power monitoring schemes to reduce the power consumption