Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Understanding Delta-Sigma Data Converters

Computer simulations are used to determine the stability limits of single-bit delta-sigma modulators up to order 8. It is found that none of the existing criteria for stability are adequate for design. Plots of the maximum signal-to-noise ratio (SNR) achievable with a given modulator order and oversampling ratio (OSR) are presented. These graphs can be used to determine the modulator order and OSR required to achieve a given SNR or to check the tightness of (as yet unavailable) theoretical bounds. >

An empirical study of high-order single-bit delta-sigma modulators

CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

A hearing compensation system for the hearing impaired comprises a plurality of bandpass filters having an input connected to an input transducer and each bandpass filter having an output connected to the input of one of a plurality of multiplicative AGC circuits whose outputs are summed together and connected to the input of an output transducer. The multiplicative AGC circuits attenuate acoustic signals having a constant background level without the loss of speech intelligibility. The identification of the background noise portion of the acoustic signal is made by the constancy of the envelope of the input signal in each of the several frequency bands. The background noise that will be suppressed includes multi-talker speech babble, fan noise, feedback whistle, fluorescent light hum, and white noise.

Hearing aid device incorporating signal processing techniques

Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in next-generation FPGAs is therefore crucial.
This dissertation examines the architecture of FPGAs with memory, as well as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory, as well as the automated random generation of such circuits, the architecture and algorithms for stand-alone configurable memory devices, and architectures and algorithms for the embedding of memory arrays in an FPGA.
We first present statistics gathered from 171 circuits with memory. These statistics include the number of memories in each circuit and the width and depth of these memories. We identify common interconnect patterns between memory and logic. These statistics are then used to develop a circuit generator that stochastically generates realistic circuits with memory that can be used as benchmark circuits in architectural studies.
Next, we consider the architecture of a stand-alone configurable memory that is flexible enough to implement memory configurations with different numbers of memories, memory widths and depths. Instrumental in this work is the algorithms that map memory configurations to the device. These algorithms are used in an experimental framework to investigate the effect of various architectural parameters on the flexibility, chip area, and access time of the configurable memory.
Finally, the architecture of an FPGA containing both embedded memory arrays and logic elements is considered, along with new automatic placement and routing algorithms that map circuits to the FPGA. We show that only 4 switches per memory block pin are required in the interconnection between the memory arrays and logic elements, and even lower in FPGAs with four or fewer memory arrays. In addition, we show that by providing direct connections between memory arrays, the FPGA density can be improved slightly, and the average memory access time can be improved by as much as 25%.

Architectures and algorithms for field-programmable gate arrays with embedded memory

A method for designing stable 1-b high-order (>or=3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizer's gain in the modulator at the present clock period determines the modulator's stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64. >

Design of stable high order 1-bit sigma-delta modulators

A fourth order switched capacitor sigma-delta modulator architecture is presented providing extremely high signal to quantization noise ratio with modest circuit level demands for digital audio specification. Tolerable nonidealities in subcircuits are specified by system level simulation. The subcircuits are designed to fulfil the digital audio specification. Five modulators are fabricated in order to investigate the 1/f-noise elimination. >

Fourth order sigma-delta modulator circuit for digital audio and ISDN applications

A sigma-delta analog/digital (A/D) converter realization using a two-stage fourth-order modulator architecture and a fifth-order digital running-sum decimation filter is presented. The analog part of the converter consists of two cascaded second-order modulators. Scaling is used between the sections in order to achieve the modest requirements for component matching and the integrator's gain and phase. A digital running-sum filter is used for the decimation to 4f/sub s/ or 2f/sub s/. A dedicated seven-instruction filter processor is designed to perform the final decimation and I/O-communication. The whole system operates on a single 5-V operation voltage. >

An oversampled sigma-delta A/D converter circuit using two-stage fourth order modulator

A class of efficient linear-phase finite impulse response (FIR) decimators for attenuating the out-of-band noise generated by a high-order sigma-delta analog-to-digital modular is introduced. The stopband attenuation of these decimators is more than 120 dB. The decimators contain no general multipliers and a few data memory locations, thereby making them easily VLSI-realizable. This is achieved by using several decimation stages, with each stage containing a small number of delays and arithmetic operations. Some of the stages are constructed using low-order building blocks which are combined to give a selective filter using a few additional tap coefficients and adders. The output sampling rate of these decimators is the minimum possible one, and the proposed decimators can be used, with very slight changes, for many oversampling ratios. These decimators highly attenuate the undesired out-of-band signal components of the input signal, thus significantly relaxing the antialiasing prefilter requirements. >

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Multiplier-free decimator algorithms for superresolution oversampled converters

The authors present a high-performance second-order sigma-delta modulator for modem and ISDN (integrated-services digital network) analog-to-digital (A/D) conversion applications. The major performance design limiting factors are demonstrated. It is shown that a true 16-bit A/D converter with single 5-V power supply for voice band can be realized with an oversampling ratio of 512; and a 16-bit dynamic range is achieved with an oversampling ratio of 256. The die size of the proposed modulator, using 2.5- mu m CMOS technology, is only 0.56 mm/sup 2/. >

http://ieeexplore.ieee.org/iel2/706/573/00015409.pdf

T. Karema

Papers

Design of stable high order 1-bit sigma-delta modulators

Fourth order sigma-delta modulator circuit for digital audio and ISDN applications

An oversampled sigma-delta A/D converter circuit using two-stage fourth order modulator

Multiplier-free decimator algorithms for superresolution oversampled converters

Fully differential CMOS sigma-delta modulator for high performance analog-to-digital conversion with 5 V operating voltage