SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

Multistability and hysteresis are widely occurring phenomena in devices, leading to many misconceptions among compact model developers. In this paper, we show how hysteretic devices can be modelled in general using only continuous/smooth primitives in a differential equation format suitable for simulation, and how the models can be implemented properly in languages like Verilog-A and ModSpec (MATLAB®). Apart from the generic formalism, several concrete device examples are described and analyzed, including a new compact model for ESD protection devices, new memristor models, a simplified electro-thermal model for HBTs, and a modified Stoner-Wohlfarth model for ferromagnets. Common features of these models are studied to further illustrate the modelling methodology for multistability and hysteresis in devices.

Modelling multistability and hysteresis in ESD clamps, memristors and other devices

This paper presents a novel technique for modeling the electrostatic discharge snapback phenomenon in integrated circuits (ICs). The macromodel is built using standard components: BSIM3v3.2 model for the MOSFET, a bipolar transistor modeled by Mextram 504.7, and a substrate resistor. The IC under test is characterized by its die and package impedance. The model should allow easier simulation program with IC emphasis implementation, high simulation speed, less convergence issues, and wider availability of a gate-grounded n-type MOSFET protection device. Our model determines the interaction between the protection device and the internal circuitry of the IC. The model parameters are extracted with MATLAB script. Simulation results are compared with transmission-line pulsing measurement for a voltage regulator NCV4949 and a controller area network transceiver TLE6250G.

Modeling IC Snapback Characteristics Under Electrostatic Discharge Stress

Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models

The modeling of ESD devices, such as MOS transistors, under ESD stress and bias conditions is reviewed A practical macro-modeling approach composed of industry standard BJT and MOS compact models is presented SPICE-type circuit level simulations that uses these models is demonstrated These include examples at both the I/O cell as well as full-chip levels Predicting ESD circuit performance as well as the inherent circuit simulation challenges are discussed

ESD Simulation using Compact Models: from I/O Cell to Full Chip

A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog-A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved.

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only, mainly a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. It offers advantages of convenience in CAD implementation, high simulation speed, wider availability, and less convergence issues. The modeling approach has been used to investigate rise-time effects in TLP stress testing. The simulation, as well as measurement, demonstrated that the rising edge of TLP pulse affects snapback trigger voltage Vt1 not only in gate coupled NMOS but also grounded gate NMOS devices. It implies that the base transit time and the junction capacitance of parasitic BJT have impact on trigger voltage Vt1.

/pdf/modeling-snapback-and-rise-time-effects-in-tlp-testing-for-5cjk05nygc.pdf

T. Luk

Papers

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models