For designers of large-scale parallel computers, it is greatly desired that performance of parallel applications can be predicted at the design phase. However, this is difficult because the execution time of parallel applications is determined by several factors, including sequential computation time in each process, communication time and their convolution. Despite previous efforts, it remains an open problem to estimate sequential computation time in each process accurately and efficiently for large-scale parallel applications on non-existing target machines.This paper proposes a novel approach to predict the sequential computation time accurately and efficiently. We assume that there is at least one node of the target platform but the whole target system need not be available. We make two main technical contributions. First, we employ deterministic replay techniques to execute any process of a parallel application on a single node at real speed. As a result, we can simply measure the real sequential computation time on a target node for each process one by one. Second, we observe that computation behavior of processes in parallel applications can be clustered into a few groups while processes in each group have similar computation behavior. This observation helps us reduce measurement time significantly because we only need to execute representative parallel processes instead of all of them.We have implemented a performance prediction framework, called PHANTOM, which integrates the above computation-time acquisition approach with a trace-driven network simulator. We validate our approach on several platforms. For ASCI Sweep3D, the error of our approach is less than 5% on 1024 processor cores. Compared to a recent regression-based prediction approach, PHANTOM presents better prediction accuracy across different platforms.

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PHANTOM: predicting performance of parallel applications on large-scale parallel machines using a single node

Programming Petascale Applications with Charm

We present an end-to-end simulation framework that is capable of simulating High-Performance Computing (HPC) systems with hundreds of thousands of interconnected processors. The tool applies discrete event simulation and is driven by real-world application traces. We refer to it as MARS (MPI Application Replay network Simulator). It maintains reasonable simulation details of both the processors in general and specifically the interconnection network. Among other things, it features several network topologies, flexible routing schemes, arbitrary application task placement, point-to-point statistics collection, and data visualization. With a few case studies, we demonstrate the usefulness of this tool for assisting high-level system design as well as for performance projection and application tuning of future HPC systems.

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A framework for end-to-end simulation of high-performance computing systems

We present an end-to-end simulation framework that is capable of simulating High-Performance Computing HPC systems with hundreds of thousands of interconnected processors. The tool applies discrete event simulation and is driven by real-world application traces. It provides a semantically correct replay of MPI application traces and maintains reasonable simulation details of both the processors in general and the interconnection network in particular. Among other things, it features several interconnection network topologies, flexible routing schemes, arbitrary application task placement, point-to-point statistics collection, and data visualization. With a few case studies, we demonstrate the usefulness of this tool for assisting high-level system design as well as for performance projection and application tuning of future HPC systems.

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A Framework for End-to-End Simulation of High-performance Computing Systems

Communication traces are increasingly important, both for parallel applications' performance analysis/optimization, and for designing next-generation HPC systems. Meanwhile, the problem size and the execution scale on supercomputers keep growing, producing prohibitive volume of communication traces. To reduce the size of communication traces, existing dynamic compression methods introduce large compression overhead with the job scale. We propose a hybrid static-dynamic method that leverages information acquired from static analysis to facilitate more effective and efficient dynamic trace compression. Our proposed scheme, Cypress, extracts a program communication structure tree at compile time using inter-procedural analysis. This tree naturally contains crucial iterative computing features such as the loop structure, allowing subsequent runtime compression to "fill in", in a "top-down" manner, event details into the known communication template. Results show that Cypress reduces intra-process and inter-process compression overhead up to 5× and 9× respectively over state-of-the-art dynamic methods, while only introducing very low compiling overhead.

Cypress: combining static and dynamic analysis for top-down communication trace compression

Parallel computers today are designed with larger number of processors than ever before, connected by large scale interconnection networks. Communication is the key to achieving high performance on such machines, making the study of interconnection networks important. Parallel simulations of interconnection networks present a unique problem characterized by fine-grained computation and strong dependence among events. The absence of large lookaheads makes it unsuitable to use a conservative simulation. Using an optimistic parallel discrete event simulation allows us to extract reasonable parallelism from this simulation. In this paper we present BigNetSim, an interconnection network simulator. We analyze its performance and present techniques related to enhancing performance and scaling it to a large number of processors on different artificial traffic patterns and real application logs. Inspite of the overheads of a parallel optimistic simulation, we have achieved a breakeven with sequential simulation at four processors and demonstrate perfect scaling to 128 processors.

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T. Mehta

Papers

Scaling an optimistic parallel simulation of large-scale interconnection networks