Research efforts on achieving low interfacial density of states (Dit) as well as low electrical leakage currents on GaAs-based III–V compound semiconductors are reviewed. Emphasis is placed on ultra high vacuum (UHV) deposited Ga2O3(Gd2O3) and atomic layer deposition (ALD)-Al2O3 on GaAs and InGaAs. Ga2O3(Gd2O3), the novel oxide, which was electron-beam evaporated from a gallium-gadolinium-garnet target, has, for the first time, unpinned the Fermi level of the oxide/GaAs heterostructures. Interfacial chemical properties and band parameters of valence band offsets and conduction band offsets in the oxides/III–V heterostructures are studied and determined using X-ray photoelectron spectroscopy and electrical leakage transport measurements. The mechanism of III–V surface passivation is discussed. The mechanism of Fermi-level unpinning in ALD-Al2O3ex-situ deposited on InGaAs were studied and unveiled. Systematic heat treatments under various gases and temperatures were studied to achieve low leakage currents of 10-8–10-9 A/cm2 and low Dit's in the range of (4–9)×1010 cm-2 eV-1 for Ga2O3(Gd2O3) on InGaAs. By removing moisture from the oxide, thermodynamic stability of the Ga2O3(Gd2O3)/GaAs heterostructures was achieved with high temperature annealing, which is needed for fabricating inversion-channel metal–oxide–semiconductor filed-effect transistors (MOSFET's). The oxide remains amorphous and the interface remains intact with atomic smoothness and sharpness. Device performances of inversion-channel and depletion-mode III–V MOSFET's are reviewed, again with emphasis on the devices using Ga2O3(Gd2O3) as the gate dielectric.

https://iopscience.iop.org/article/10.1143/JJAP.46.3167/pdf

III–V Metal–Oxide–Semiconductor Field-Effect Transistors with High κ Dielectrics

Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.

High speed GaAs integrated circuits

A systematic experimental and theoretical study was performed to determine the causes of oxide-induced Fermi level pinning and unpinning on GaAs(001)-c(2×8)∕(2×4). Scanning tunneling spectroscopy (STS) and density functional theory (DFT) were used to study four different adsorbates’ (O2, In2O, Ga2O, and SiO) bonding to the GaAs(001)-c(2×8)∕(2×4) surface. The STS results revealed that out of the four adsorbates studied, only one left the Fermi level unpinned, Ga2O. DFT calculations were used to elucidate the causes of the Fermi level pinning. Two distinct pinning mechanisms were identified: direct (adsorbate induced states in the band gap region) and indirect pinnings (generation of undimerized As atoms). For O2 dissociative chemisorption onto GaAs(001)-c(2×8)∕(2×4), the Fermi level pinning was only indirect, while direct Fermi level pinning was observed when In2O was deposited on GaAs(001)-c(2×8)∕(2×4). In the case of SiO on GaAs(001)-c(2×8)∕(2×4), the Fermi level pinning was a combination of the two mech...

Electronic properties of adsorbates on GaAs(001)-c(2×8)∕(2×4)

Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a beating on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. MOSFET diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-µm calls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary.

Trends in advanced process technology&#8212;Submicrometer CMOS device design and process requirements

Atomically smooth Ga2O3(Gd2O3)∕GaAs interface with low interfacial density of states and low electrical leakage currents have been achieved after the heterostructures were air exposed and tailor annealed to ∼750°C. The heat treatments, with annealing at an intermediate temperature of ∼300°C as a necessary step, were carried out under ultrahigh vacuum (UHV) and via standard rapid thermal annealing with flow of pure nitrogen gas. Furthermore, the oxide remains amorphous and minimal interfacial reaction occurred between the oxide and substrate, critical aspects for device performance. Studies using x-ray reflectivity and high-resolution transmission electron microscopy show that the interfacial roughness is <0.2 and <0.4nm for annealing under UHV and non-UHV, respectively. Electrical measurements on the metal-oxide-semiconductor diodes have exhibited low leakage currents (10−8–10−9A∕cm2), a dielectric constant of ⩾14, and a low interfacial density of states (Dit) of <1012cm−2eV−1.

http://web.phys.ntu.edu.tw/mhong/SCI/2006/Structural%20and%20electrical%20characteristics%20of%20Ga2O3(Gd2O3)GaAs%20under%20high%20temperature%20annealing.pdf

Structural and electrical characteristics of Ga2O3(Gd2O3)∕GaAs under high temperature annealing

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.

T. Mimura

Papers

Planar GaAs MOSFET integrated logic