Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.

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Signal Sampling Based Transition Modeling for Digital Gates Characterization

Investigation on BIST assisted failure analysis on digital integrated circuits

ment. This idea is shown through the realization of a biquadratic filter for a bandpass sigma-delta modulator. In addition, a family of half-delay switched-opamp integrator and modulator sigma-delta modulators with a strong reduction on power consumption are reported and commented. The book is the first that discuss of this topic and can be found interesting both for specialists in the topic and for postgraduate students who are already familiar with CMOS analog circuits. Gaetano Palumbo

http://ieeexplore.ieee.org/iel5/101/32094/01492720.pdf

T. Ndjountche

Papers

Digital Logic Testing and Simulation [Book Review]