In this paper, a power-efficient 16times 16 configurable Booth multiplier (CBM) that supports single 16-b, single 8-b, or twin parallel 8-b multiplication operations is proposed. To efficiently reduce power consumption, a novel dynamic-range detector is developed to dynamically detect the effective dynamic ranges of two input operands. The detection result is used to not only pick the operand with smaller dynamic range for Booth encoding to increase the probability of partial products becoming zero but also deactivate the redundant switching activities in ineffective ranges as much as possible. Moreover, the output product of the proposed multiplier can be truncated to further decrease power consumption by sacrificing a bit of output precision. To efficiently and correctly combine these techniques, some additional components, including a correcting-vector generator, an adjustor, a sign-bit generator, a modified error compensation circuit, etc., are also developed. Finally, three real-life applications are adopted to evaluate the power efficiency and error performance of the proposed multiplier. The results show that the proposed multiplier is more complex than non-CBMs, but significant power and energy savings can be achieved. Furthermore, the proposed multiplier maintains an acceptable output quality for these applications when truncation is performed.

Design of Power-Efficient Configurable Booth Multiplier

Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.

/pdf/fast-power-and-slew-aware-gated-clock-tree-synthesis-492u9fessm.pdf

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36p lower than those reported in the best previous work in the literature.

Low-power gated and buffered clock network construction

Clock root gating transformation targets power savings on the clock tree by inserting gating logic at the root of the clock. In this paper, we propose an efficient graph-based algorithm to solve the root clock gating optimization problem. The algorithm is also tightly integrated with a clock tree synthesis tool so that real power savings can be achieved after the clock tree is generated. Experimental results on industrial circuits showed that significant power savings can be achieved.

/pdf/power-minimization-by-clock-root-gating-4lvivjhhlu.pdf

Power minimization by clock root gating

Wordlength determination is an indispensable task in digital hardware implementations of signal processing algorithms because the wordlength affects power consumption and system performance. There is a tradeoff between power consumption and system performance when searching for the optimum wordlength. We have developed a technique of dynamically controlling the wordlength used in the signal processing algorithms of wireless orthogonal frequency-division multiplexing (OFDM) receivers. The receiver dynamically changes the wordlength on the basis of the conditions in the propagation environment while satisfying the user-required communication quality. That is, the system optimizes the wordlength while operating by sensing its own performance and gradually adjusting this wordlength to improve performance. Testing revealed that, for a packet error rate (PER) of 10-2 , the application of this technique to an OFDM receiver reduces energy dissipation by 18.1%-30.2%.

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

/pdf/a-clock-gating-method-for-low-power-lsi-design-5cp0auc1w6.pdf

T. Ueda

Papers

A clock-gating method for low-power LSI design