High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV resistance-capacitance (RC) parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wire length, clock power, slew, and skew in 3D clock network design. Second, we develop a two-step 3D clock tree synthesis method: 1) 3D abstract tree generation based on the three-dimensional method of means and medians (3D-MMM) algorithm; 2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: 1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case, 2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases, and 3) our 3D-MMM-ext method finds a close-to-optimal design point in the “TSV count versus power consumption” tradeoff curve very efficiently.

Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

Three methods have been proposed to test Through-Silicon-Vias (TSV) electrically prior to 3D integration. These test methods are (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests are aimed at detecting one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate a 1 bit pass/fail signal. The outputs are streamed out through a scan chain. The test time is 10 μs for the leakage test and the sense amplification methods, and is 15 μs for the capacitive bridge method. All these methods can be implemented for test-before-stacking, which will increase assembled yield. Resolution, power and area of these TSV test circuits were compared. The performance of each circuit was studied at PVT corners. The IMEC TSV technology was assumed, and the designs were simulated using the 32 nm predicted device model. Without any failure, the TSV capacitance's mean value is 37 fF, and its leakage resistance is higher than 850 M?. With respect to 37 fF standard capacitance, resolution for the sense amplification method is 3.3 fF (8.9%); it is 0.16 fF (0.4%) for the capacitance bridge method. Although the capacitance bridge method has relatively better resolution, it takes 4x area and 10x power than the other two, and is also more sensitive to PVT variation. Resolution of the leakage current monitor method is 10 M? (1.1%) with respect to its threshold 850 M?, and use 42.5aJ power in normal case. Sense amplification circuit can be modified to detect equivalent leakage resistance under 2K?.

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model is developed for signal TSVs in 3-D IC. With consideration of liner material and also stress, a nonlinear model is established between electrical delay with temperature and stress. Moreover, sensitivity analysis is performed to relate the reduction of temperature and stress gradients with respect to dummy TSVs insertion. Taking the design of 3-D clock tree as a case study, we have formulated a nonlinear optimization problem for clock-skew reduction. By allocating dummy TSVs to reduce the temperature and stress gradients, the clock skew introduced by signal TSVs and drivers can be minimized. A number of 3-D clock-tree benchmarks are utilized in experiments. We have observed that with the use of dummy TSV insertion, clock skew can be reduced by 61.3% on average when the accurate nonlinear electrical-thermal-mechanical delay model is applied.

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D integration technology emerges as a viable option to improve chip performance and increase device density in a direction orthogonal to costly device scaling. As 3D integration is becoming a promising technology for next-generation chip design, recent years have seen a huge proliferation of research literature exploiting it from a security perspective. This paper presents a survey on the current state of 3D integration technology from a security perspective and summarizes its security opportunities and challenges. We report current research work on 3D integration based security in three major applications: supply chain attack prevention, side-channel attack mitigation, and trustworthy computing system design. The security advantages and opportunities of 3D integration in these security applications are highlighted. Besides, the paper discusses new vulnerabilities risen by 3D integration that require researchers’ attention. Based on the survey result, we summarize the distinct characteristics of 3D ICs and investigate their impacts on security-aware 3D IC designs.

Security and Vulnerability Implications of 3D ICs

This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

https://www.aspdac.com/aspdac2010/Archive_Folder/pdf/6A-4.pdf

Clock tree embedding for 3D ICs

This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the prebond testability by allocating specially designed resources called TSV-buffers and redundant trees with transmission gates. We proposes viable solutions to the two fundamental problems of the previous work: (1) using much less buffer resources by preventing (potentially 'bad') TSV-buffers with a new tree topology generation algorithm; (2) completely removing the transmission gate control lines by using a specially designed component called self controlled clock transmission gate (SCCTG). Compared to the existing 3D tree topology generation algorithms, solution 1 can use 56%--88% less number of TSVs, 53%--67% less number of buffers, 22%--65% less total wirelength, and 26%--43% less clock power for the benchmark circuits with dense sink placements. Moreover, solution 2 reduces the total wirelength of all the benchmark circuits by 17% and 23% on average for the 2-die and 4-die stacked 3D ICs, respectively.

Clock tree synthesis with pre-bond testability for 3D stacked IC designs

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D (deferred layer embedding for 3D ICs), which optimally finds the embedding layers of tree nodes, so that the TSV cost required for a tree topology is minimized, and DME-3D (deferred merge embedding for 3D ICs), which is an extended algorithm of the 2D merging segment, to minimize the total wirelength in 3D design space, with the consideration of the TSV effect on delay. In addition, when an abstract tree topology is not given, we propose NN-3D (nearest neighbor selection for 3D ICs), which constructs a (TSV and wirelength) cost-effective abstract tree topology for 3D ICs. Through experimentation, we have confirmed that the clock tree synthesis flow using the proposed algorithms is very effective, outperforming the existing 3D clock tree synthesis in terms of the number of TSVs, total wirelength, and clock power consumption.

Clock Tree synthesis for TSV-based 3D IC designs

This paper addresses a bounded skew clock routing problem in 3D stacked IC designs to enable effective trade-offs between power and clock skew. The existing 3D clock tree synthesis (CTS) techniques for power and temperature management solve the clock routing problem in two steps: (step 1) constructing a zero skew clock tree and (step 2) restructuring the clock tree to minimize the increased clock skew caused by temperature variation. Unlike the previous works, this paper provides various solutions for step 1 by relaxing skew bound rather than one (possibly extreme) solution, so that the task of step 2 is more amenable and effective by reduced or controlled power in step 1. To this end, we propose an algorithm, called BSTDME-3D (bounded skew clock tree with deffered merge embedding for 3D ICs), to solve the bounded skew clock tree embedding problem in 3D ICs for a given tree topology. By utilizing the proposed clock tree embedding algorithm, we setup the (un)buffered 3D CTS flow under a (non-)zero skew bound, and study impacts of skew bound on total wirelength and thus clock power consumption. From the extensive experiments, it is shown that the unbuffered CTS with 100ps skew bound reduces 3D clock wirelength by 16% on average for the 4-die stacked 3D ICs. The buffered CTS with 100ps skew bound reduces 3D clock wirelength by 18%, buffer resource by 25%, and thereby clock power consumption by 16% on average for the 4-die stacked 3D ICs.

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

Tak-Yung Kim

Papers

Clock tree embedding for 3D ICs

Clock tree synthesis with pre-bond testability for 3D stacked IC designs

Clock Tree synthesis for TSV-based 3D IC designs

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew

Post Silicon Management of On-Package Variation Induced 3D Clock Skew