A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.

DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.

Access request control apparatus which reassigns higher priority to incomplete access requests

A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses Priority resolver circuits award access to main memory on a predetermined priority basis Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors

Asynchronous multiport parallel access memory system for use in a single board computer system

A priority resolver shortens the time between a requesting circuit initiating a request for access to a requested circuit that is shared with other circuits and the requesting circuit actually functioning with the requested circuit. A first portion of the priority resolver circuit is associated with the requesting circuit and makes a request for access to another portion of the priority resolver circuit associated with the requested circuit before the first portion has chosen the highest priority one of a plurality of requesting circuits that have concurrently bid for access to the requested circuit. Before the portion of the priority resolver associated with the requested circuit can respond to the access request and return an access grant signal, the first portion of the priority resolver circuit has chosen the highest priority requesting circuit. In this manner the time for accessing requested circuits is decreased.

Two-level priority arbiter generating a request to the second level before first-level arbitration is completed

With a view to reducing the congestion of a pipeline for cache memory access in, for example, a multi-core system, a cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Cache memory control device and pipeline control method

PURPOSE:To expand a usable range by forming plural pairs of registers for holding the base address value and threshold address value of a storage area in a main storage device and using these registers for two different address checking methods of virtual computers. CONSTITUTION:The leading address (''0'' e.g.) of the main storage area is set up in base registers 2-1, 3-1. The size of the whole areas to be used for the 2nd virtual calculation system and the size of an area assigned to a real main storage virtual computer are set up in threshold registers 2-2, 3-2 respectively. For an access request to the real main storage virtual computer which specifies a discrimination No.10, address formation and monitoring are executed by the base register 3-1 and the threshold register 3-2 in the normal method. As to an access request to another virtual computer specifying an identification No.01, the existence of addresses in a section between the threshold registers 3-2 and 2-2 is especially checked.

Address check system

PURPOSE:To decrease the access processing time for a device with a shorter cycle, by selecting one device out of access request devices with longer clock cycle at first, and making selection between the device and an access request device with shorter clock cycle with priority. CONSTITUTION:When an access request signal of access request devices CHP0- 3 having longer clock cycle is inputted to CHP ports 2-5, simultaneously address information and control information are inputted to CHP ports 22-25 and one of the request signals is selected at a priority selection circuit 1. The selection signal from the circuit 1 is applied to the 2nd priority selection circuit 8. To this circuit 8, a request signal from access request devices CPU0-1 with shorter clock cycle is inputted via CPU ports 10 and 11. Finally, one request signal is selected and the address information and the control information are selected at the 2nd selector 28.

Selection circuit for priority

PURPOSE:To process a memory access request whose clock is different, without increasing the number of hardwares, by constituting a pipeline of an even number of stages, and always deciding a degree of priority by a clock of an even cycle at the time of loop-back. CONSTITUTION:A titled device is provided with a channel processor use priority circuit 1 for selecting an access request of a 2tau clock from channel processors CHP0-n, a priority circuit 2 for selecting an access request of 1tau clock from CPUs 0-m, and selectors 3, 4 for selecting an output from the circuits 1, 2. Also, each stage 21-27 of a pipeline which has an even number of stages and shifts its contents at every 1tau clock is provided. In this way, at the time of loop- back from a loop-back control part 8, a degree of priority of an even cycle is always decided by a data pool control part 11, etc., and a memory access request whose clock is different is processed without increasing the number of hardware.

Access processor of pipeline processing system

PURPOSE:To reduce LRU bits by dividing associative levels into plural groups, performing LRU logical operation in each group and reduces the number of LRU bits, and providing tripled flag bits separately and making a majority decision. CONSTITUTION:For example, eight associative levels are divided into a group 6-1 of levels 0-3 and a group 6-2 of levels 4-7. The LRU logical operation is performed in each group. Further, an H/C (hop and cold) bit 8 for indicating which group is to be replaced is provided and tripled to provide three HCO- HC2, making a majority decision. Consequently, while the associative levels are increased, the LRU bits are minimized and the buffer performance is prevented from deteriorating even in case of error occurrence.

Lru control system of buffer storage device

PURPOSE:To attain efficient storage access processing, by performing revision processing of a control memory in parallel with the write of buffer, only when the buffer collating information in the control memory is required for revision. CONSTITUTION:When a partial write instruction is received in an interface register 4 of a data processor CPU0, a control memory 20 checks the correspondence of data of collating information between a buffer of each CPU and a buffer 14 of a storage controller is checked at the control memory 20. When a BI logical circuit 24 detects ''1'' at an area other than the CPU0, and an instruction BIRQ making the data ineffective is transmitted to the buffer of the CPU corresponding to ''1''. Through the instruction from the circuit 24, a reapplication logical circuit 25 sets a write signal to a buffer 14 together with a pipeline reapplication request for the revision of the memory 20 to a pipeline constituent 13. This request passes through a priority control circuit 6 from the element 13, performs write control for the buffer 14 and revises the memory 20 via pipeline constituents 7, 8.

Takahashi Masanori

Papers

Address check system

Selection circuit for priority

Access processor of pipeline processing system

Lru control system of buffer storage device

Storage access processor