Access processor of pipeline processing system

TLDR: In this article, a pipeline of an even number of stages is proposed to process a memory access request whose clock is different, without increasing the number of hardwares, by constituting a pipeline, and always deciding a degree of priority by a clock at the time of loop-back.

Abstract: PURPOSE:To process a memory access request whose clock is different, without increasing the number of hardwares, by constituting a pipeline of an even number of stages, and always deciding a degree of priority by a clock of an even cycle at the time of loop-back. CONSTITUTION:A titled device is provided with a channel processor use priority circuit 1 for selecting an access request of a 2tau clock from channel processors CHP0-n, a priority circuit 2 for selecting an access request of 1tau clock from CPUs 0-m, and selectors 3, 4 for selecting an output from the circuits 1, 2. Also, each stage 21-27 of a pipeline which has an even number of stages and shifts its contents at every 1tau clock is provided. In this way, at the time of loop- back from a loop-back control part 8, a degree of priority of an even cycle is always decided by a data pool control part 11, etc., and a memory access request whose clock is different is processed without increasing the number of hardware.