An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A process is provided for fabricating MOSFET devices having field source, gate and drain regions. The threshold voltage of both the channel and field regions of such devices is controlled by forming a comparatively thick oxide film on a semiconductor surface, defining enhancement mode transistor regions in the oxide film to expose portions of the semiconductor surface, implanting p-type ions under conditions such that the peak distribution of p-type atoms lies in the semi-conductor substrate just beneath the semiconductor/-oxide interface and counter-doping with n-type ions under conditions such that no implanted ions penetrate the oxide film. As a consequence, a desirably high threshold voltage is obtained in the field region, while a desirably low threshold voltage is obtained in the channel region. Depletion mode transistors are fabricated on the same wafer by masking the enhancement mode regions, defining depletion mode transistor regions in the oxide film to expose portions of the semiconductor surface and implanting n-type ions under conditions such that no ions penetrate the mask or oxide film. Metal gate or refractory gate technology is then employed to fabricate source, gate and drain regions and electrical contacts thereto. Parasitic conduction paths between neighboring transistors are substantially eliminated due to the peak distribution of p-type atoms in the field region.

Method of controlling MOSFET threshold voltage with self-aligned channel stop

A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

Floating-gate memory cell with tailored doping profile

A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Non-volatile metal nitride oxide semiconductor device

A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.

Semiconductor device and a method for fabricating the same

A method of forming a shallow P-N junction under precise control of its position. An impurity doped layer of the first conductivity type is formed, so that the impurity concentration may become a maximum at substantially the surface of a semiconductor substrate or at an inner part of the semiconductor substrate. Ions of impurities of a second conductivity type, opposite to the first conductivity type, are implanted, so that the impurity concentration may become a maximum greatest at the maximum depletion layer thickness in the semiconductor substrate. The P-N junction finally formed is located within the maximum depletion layer thickness.

Takashi Tsuchimoto

Papers

Method of manufacturing semiconductor device