An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Isolation trenches, formed on a silicon substrate, are lined with a silicon nitride liner and filled with an insulating filler for isolating MOS transistors from each other. For each MOS transistor, an impurity-doped channel region is formed between adjacent trenches, the channel region having a conductivity type equal to conductivity type of the substrate and a concentration higher than a concentration of the substrate. For each channel region, a pair of heavily doped impurity regions are formed in locations close to the adjacent trenches. The heavily doped regions have a concentration higher than the concentration of the channel region.

Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages

In order to increase a multiprocessing speed, a cache memory is provided with a dual ported storage section so as to be independently accessible by a processor allocated to the cache memory and by another cache memory. The dual ported storage section saves tag addresses and valid tag address information. Each of the tag addresses corresponds to data stored in a data storage section which forms part of the cache. One of two comparators coupled to the dual ported storage section checks to see if an address updated by another cache is in the cache. When this happens, the valid tag address information of the address is invalidated.

Cache memory for use with multiprocessor systems

PROBLEM TO BE SOLVED: To prevent a drop in a threshold voltage (Vth) at a channel region end of a MOSFET isolated by an STI structure, in the gate widthwise direction and a manufacturing unevenness. SOLUTION: In a stage for forming an insulating isolation region 24, having a silicon nitride film liner 28 isolating an MOSFET, a p-type impurity region 33 of the same conductivity type as that of and more highly concentrated than a channel region 32 is formed before a silicon oxide film spacer 44 is constituted in the inner wall of the opening in a silicon nitride film 40. After the formation of the silicon oxide film spacer 44, a trench 22 is formed in a silicon substrate 21, with the spacer 44 serving as a mask. Furthermore, a silicon nitride film liner 28 is formed inside of the trench 22, after removal of the silicon oxide film spacer 44.

Semiconductor device and its manufacturing method

A memory circuit having an improved redundant structure which can operate with low power consumption. A plurality of program cells to store information identifying faulty memory cells. Each of the program cells is composed of a first series circuit of a program element and a first transistor of a first conductivity and a second series circuit of a second transistor of a second conductivity type and a third transistor of the first conductivity type, gates of the second and third transistors being connected to an intermediate junction of the first series circuit and a gate of the first transistor being connected to an intermediate junction of the second series circuit.

Memory circuit with improved redundant structure

@ A memory circuit provided with a control circuit which controls operations of the memory circuit in such a manner that the memory circuit is automatically set in a stand-by state when a value of a power voltage is reduced in absolute value irrespectively of a control signal from the outside and which consumes no DC current is disclosed. The control circuit comprises a load element coupled between first and second terminals, a series circuit of first and second field effect transistors coupled between the second terminal and a third terminal, the first transistor being controlled by the control signal, the second transistor being adapted to be conducting when a value of the power voltage is sufficient for allowing a normal access operation, a means for connecting the first terminal to one of the power voltage and a reference voltage, and a means for connecting the third terminal to the other of the power voltage and the reference voltage.

Takayuki Watanabe

Papers

Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages

Cache memory for use with multiprocessor systems

Semiconductor device and its manufacturing method

Memory circuit with improved redundant structure

Memory circuit with power supply voltage detection means