Patent
Cache memory for use with multiprocessor systems
TLDR
In this paper, a cache memory is provided with a dual ported storage section so as to be independently accessible by a processor allocated to the cache memory and by another cache memory, in order to increase a multiprocessing speed.Abstract:
In order to increase a multiprocessing speed, a cache memory is provided with a dual ported storage section so as to be independently accessible by a processor allocated to the cache memory and by another cache memory. The dual ported storage section saves tag addresses and valid tag address information. Each of the tag addresses corresponds to data stored in a data storage section which forms part of the cache. One of two comparators coupled to the dual ported storage section checks to see if an address updated by another cache is in the cache. When this happens, the valid tag address information of the address is invalidated.read more
Citations
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Patent
Multi-processor system having a multi-port cache memory
TL;DR: In this paper, a multi-port cache memory of multicore memory structure is connected to and shared with a plurality of processors, and two sets of interface signal lines, for instruction fetch and for data read/write, to each processor.
Patent
Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
TL;DR: In this article, the cache controller includes a set of latches coupled to the host bus which it uses to latch the state of host bus during a snoop cycle if the cache is unable to immediately snoop that cycle.
Patent
Computer cache memory windowing
TL;DR: Cache windowing as mentioned in this paper divides a large level 1 cache into smaller sizes called windows, allowing the cache to provide more data faster to the CPU, and provides high CPU utilization rates for those processing applications where locality of memory references is poor.
Patent
Apparatus and method for maintaining processing consistency in a computer system having multiple processors
TL;DR: In this paper, an apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively is presented. But it does not address the problem of processor ordering violation.
Patent
Coherent copyback protocol for multi-level cache memory systems
TL;DR: In this paper, the authors propose a coherent copyback protocol for multi-level cache memory systems, which prevents more than one modification from existing in multiple locations and saves access time and data bandwidth.
References
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Patent
Three level memory hierarchy using write and share flags
TL;DR: In this paper, a multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory.
Patent
System for independent cache-to-cache transfer
TL;DR: In this paper, a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP are presented.
Patent
Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
TL;DR: A 32-bit central processing unit with a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors as mentioned in this paper.
Patent
Duplicate tag store for cached multiprocessor system
TL;DR: In this paper, a cached multiprocessor system operated in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access.
Patent
Multiplexed directory for dedicated cache memory system
TL;DR: In this paper, the authors propose an approach for avoiding ambiguous data in a multi-requestor computing system of the type where each of the requestors has its own dedicated cache memory.