Showing papers by "Tanay Karnik published in 2000"

Storage element with switched capacitor

Abstract: A latch includes a pair of inverters cross-coupled between a storage node and a feedback node A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor is coupled to the feedback node when the latch holds data and is not coupled to the feedback node when the latch is loading The capacitor reduces the latch's susceptibility to soft errors when holding data, and does not appreciably slow the latch when data is loading The capacitor is implemented using the gate capacitance of complementary transistors A flip-flop includes cascaded latches, one or more of which have a switched capacitor on a feedback node

Storage element with stock node capacitive load

Abstract: A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the storage node when the storage element holds data and is not coupled to the storage node when the storage element is loading. The capacitive load reduces the storage element's susceptibility to soft errors when holding data, and does not appreciably slow the storage element when data is loading. The capacitive load is implemented using the gate capacitance of complementary transistors connected to stack nodes within the feedback inverter. A flip-flop includes cascaded latches, one or more of which have the internal capacitance.

Voltage dependent capacitor configuration for higher soft error rate tolerance

Abstract: A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.

Method and apparatus for weak inversion mode MOS decoupling capacitor

Abstract: A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.

Verwendung einer MOS-Struktur als Entstörkondensator bei dünnen Gate-Oxiden

Abstract: Verfahren zum Verwenden einer MOS-Struktur (134) als Entstorkapazitat zwischen einem ersten, die Versorgungsspannung (V CC ) einer auf einem Halbleiterchip integrierten Schaltung (130) fuhrenden Leiter und einem zweiten, die Massespannung (V SS ) fuhrenden Leiter, wobei die MOS-Struktur (50, 60, 100, 110) in einem Substrat oder in einer in dem Substrat eingebrachten Wanne mit einem Source-Gebiet (S), einem Drain-Gebiet (D) und einem zwischen dem Source- und dem Drain-Gebiet angeordneten Gate (G), das aus einem uber einer Gate-Isolatorschicht angeordneten Gate-Leiter besteht, angeordnet ist, wobei der Gate-Leiter mit dem ersten oder zweiten Leiter verbunden ist und das Source-Gebiet (S), das Drain-Gebiet und das Substrat bzw. die Wanne (B-Bulk) mit dem anderen Leiter verbunden sind, so dass die MOS-Struktur eine Kapazitat zwischen, den beiden Leitern bildet, wobei die MOS-Struktur so mit den beiden Leitern verbunden wird, dass bei den anliegenden Spannungen (V CC , V SS ) die MOS-Strukur sich im Verarmungsmodus befindet, so dass nur wenige...