T
Terence J. Weir
Researcher at Massachusetts Institute of Technology
Publications - 21
Citations - 868
Terence J. Weir is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Josephson effect & Stripline. The author has an hindex of 10, co-authored 19 publications receiving 671 citations.
Papers
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Journal ArticleDOI
Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits
Sergey K. Tolpygo,Vladimir Bolkhovsky,Terence J. Weir,Alex Wynn,Daniel E. Oates,Leonard M. Johnson,Mark A. Gouker +6 more
TL;DR: In this article, the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200mm wafers are discussed.
Journal ArticleDOI
Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
Sergey K. Tolpygo,Vladimir Bolkhovsky,Terence J. Weir,Alex Wynn,Daniel E. Oates,Leonard M. Johnson,Mark A. Gouker +6 more
TL;DR: In this paper, the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum (SFQ) digital circuits with very large scale integration on 200-mm wafers are discussed.
Journal ArticleDOI
Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al– $\hbox{AlO}_{\rm x}\hbox{/Nb} $ Josephson Junctions for VLSI Circuits
Sergey K. Tolpygo,Vladimir Bolkhovsky,Terence J. Weir,Leonard M. Johnson,Mark A. Gouker,William D. Oliver +5 more
TL;DR: In this paper, a fabrication process for Nb/Al-AlO//////////////// x /Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200mm-wafer tool set typical for CMOS foundry.
Journal ArticleDOI
Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits
Sergey K. Tolpygo,Vladimir Bolkhovsky,Terence J. Weir,Leonard M. Johnson,Mark A. Gouker,William D. Oliver +5 more
TL;DR: A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200mm-wafer tool set typical for CMOS foundry as mentioned in this paper.
Journal ArticleDOI
Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers
Sergey K. Tolpygo,Vladimir Bolkhovsky,Terence J. Weir,C. Galbraith,Leonard M. Johnson,Mark A. Gouker,Vasili K. Semenov +6 more
TL;DR: In this article, the inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated and it has been found that the inductances per unit length of stripline and microstrip line inductors continues to grow as the inductor linwidth is reduced deep into the submicron range to the widths comparable to the film thickness.