A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High performance, superscalar-based computer system with out-of-order instruction execution

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

A multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.

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Multinode reconfigurable pipeline computer

A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine's basic operation is performing Boolean operations on huge vectors of 0's and 1's. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2k words each t bits long, is reorganized into p registers each 2k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2k /p to 2k /p2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).

SIMD machine using cube connected cycles network architecture for vector processing

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags. Upon initialization of the modifiable translation logic in the cache-memory management system, the address translations and associated system tags are loaded into the address translation logic of the cache-memory management system. Thereafter, as a part of the virtual to real address translation performed by the cache-memory management system, access modes and attributes are determined for each address translation, to provide for proper memory access of cacheable versus non-cacheable storage, etc., as part of the address translation and memory management function.

Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency

The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.

Data processing system for parallel processing of different instructions

The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Bank interleaved vector processor having a fixed relationship between start timing signals

An information processing system (10) including an arithmetic unit (13) in which an item of data is processed according to one instruction, another arithmetic unit (14) in which plural items of data are processed according to one instruction, an instruction control unit (15) for distributing corresponding instruction groups to respective ones of the arithmetic units (13, 14), and a main memory (12) for exchanging data with the instruction control unit (15) and with both arithmetic units (13, 14). In the information processing system (10), a group of instructions among the above-mentioned groups of instructions, which group is restricted by the order of priority as to the execution sequence thereof, is synchronized by specially inserting a synchronization instruction (WAIT). It is also possible to divide the above-mentioned groups of instructions into a group of instructions to be serial-processed and a group of instructions capable of being parallel-processed, as to the execution sequence thereof, by inserting a serialization-start instruction (POST) and a serialization-release instruction (SUB - WAIT).

Information processing system.

An information processing system including an arithmetic unit in which one unit of data is processed according to a corresponding one instruction, and another arithmetic unit in which a great amount of data are processed according to a corresponding instruction. Also included is an instruction controller which distributes instructions selectively to respective arithmetic units (12) and a main storage (12) which achieves two-way data communication with the arithmetic units. In the system synchronization is performed with respect to instructions, among the aforesaid instructions, which, above all, must be executed in respective fixed execution sequences, by utilizing a newly employed synchronization instruction. Further, the aforesaid instructions are classified, in dependence upon the execution sequence, into first instructions which are to be executed under a serial processing mode and second instructions which can be executed under a parallel processing mode, by inserting both a serialized-starting instruction (POST) and a serialized-releasing instruction into the aforesaid instructions.

Vector data processing system with instruction synchronization

not available for EP0053457Abstract of corresponding document: US4435765The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Tetsuro Okamoto

Papers

Data processing system for parallel processing of different instructions

Bank interleaved vector processor having a fixed relationship between start timing signals

Information processing system.

Vector data processing system with instruction synchronization

Data processing apparatus