A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine's basic operation is performing Boolean operations on huge vectors of 0's and 1's. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2k words each t bits long, is reorganized into p registers each 2k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2k /p to 2k /p2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).

SIMD machine using cube connected cycles network architecture for vector processing

of the Disclosure A multiprocessing system and method for multiprocessing disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory between the CPU. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devi-ces. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multi-tasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and faciliates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.

Computer vector multiprocessing control

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Massively parallel computer including auxiliary vector processor

A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap

Data processing system including scalar data processor and vector data processor

The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Bank interleaved vector processor having a fixed relationship between start timing signals

PURPOSE:To omit read/write of unnecessary element data and to improve processing efficiency by reading previously a mask register and by detecting nonfulfilment about elememts of ones interleaved. CONSTITUTION:Element data read from a vector register designated in an operand part of an instruction are stored successively in a read register 2, and it is then, after being delayed by a buffer register 4 by one-time slot, added to an arithmetic pipeline 5. Further, element data that are designated and read out in an next operand part are successively set in a read register 3 and are inputted into the line 5. An arithmetic result outputted from said pipeline is set in a write register 1, further is written in a vector register designated in the operand part of the instruction. Further, a mask element read from an operand register designated in the mask operand part of the instruction is read out and is set in a register 6, further the output is inputted into the line 5, thereby determining execution of an operation by the logic of the mask element.

Vector data processor

not available for EP0053457Abstract of corresponding document: US4435765The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Data processing apparatus

FUJITSU has developed pipelined supercomputers, the FACOM VP-100/200 with the latest technology and new architecture. Based on extensive analyses of application programs, the following advanced features are employed in the VP system: 1. 1) Dynamically reconfigurable vector registers with large capacity. 2. 2) Efficient vector operations for vectorizing IF-statements in DO-loops, 3. 3) High level concurrency for parallel scalar-vector and vector-vector operations, 4. 4) Powerful vectorizing compiler for utilizing the advanced features, 5. 5) Effective tuning tools to extract higher performance of application programs, and 6. 6) Keeping good affinity with general-purpose computer systems. The final goals of development of the VP system are both ease of use and higher performance for various scientific and engineering applications. These goals have been achieved successfully. This paper describes the key components to establish the ease of use and higher performance, and also describes actual performances on the VP system.

FACOM VP-100/200: Supercomputers with ease of use

PURPOSE:To transmit an instruction to an operator by a simple control, by constituting a vector register consisting of plural elements, of plural banks each. CONSTITUTION:A bank timing shift register 22 is operated in order to prescribe a bank timing, and its contents are shifted to the right at every 1 cycle. When a flip-flop (a) is logical ''1'', the bank timing is made A, and when a flip-flop (b) is logical ''1'', the bank timing becomes B. An adder using timing storage part 24 stores a bank timing used for access of #0 element by an adder 10, and a multiplier using timing storage part 25 stores a bank timig used for access of #0 element by a multiplier 11. When a vector instruction is received, an instruction control part 8 detects an idle bank timing, and informs to the processing pipe line concerned that the instruction should be executed by use of said idle bank timing.

Hiroshi Tamura

Papers

Bank interleaved vector processor having a fixed relationship between start timing signals

Vector data processor

Data processing apparatus

FACOM VP-100/200: Supercomputers with ease of use

Vector data processing device