Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

A network of Wilson-Cowan (WC) oscillators is constructed, and its emergent properties of synchronization and desynchronization are investigated by both computer simulation and formal analysis. The network is a 2D matrix, where each oscillator is coupled only to its neighbors. We show analytically that a chain of locally coupled oscillators (the piecewise linear approximation to the WC oscillator) synchronizes, and we present a technique to rapidly entrain finite numbers of oscillators. The coupling strengths change on a fast time scale based on a Hebbian rule. A global separator is introduced which receives input from and sends feedback to each oscillator in the matrix. The global separator is used to desynchronize different oscillator groups. Unlike many other models, the properties of this network emerge from local connections that preserve spatial relationships among components and are critical for encoding Gestalt principles of feature grouping. The ability to synchronize and desynchronize oscillator groups within this network offers a promising approach for pattern segmentation and figure/ground segregation based on oscillatory correlation.

Synchronization and desynchronization in a network of locally coupled Wilson-Cowan oscillators

An auditory-based feature extraction algorithm is presented. We name the new features as cochlear filter cepstral coefficients (CFCCs) which are defined based on a recently developed auditory transform (AT) plus a set of modules to emulate the signal processing functions in the cochlea. The CFCC features are applied to a speaker identification task to address the acoustic mismatch problem between training and testing environments. Usually, the performance of acoustic models trained in clean speech drops significantly when tested in noisy speech. The CFCC features have shown strong robustness in this kind of situation. In our experiments, the CFCC features consistently perform better than the baseline MFCC features under all three mismatched testing conditions-white noise, car noise, and babble noise. For example, in clean conditions, both MFCC and CFCC features perform similarly, over 96%, but when the signal-to-noise ratio (SNR) of the input signal is 6 dB, the accuracy of the MFCC features drops to 41.2%, while the CFCC features still achieve an accuracy of 88.3%. The proposed CFCC features also compare favorably to perceptual linear predictive (PLP) and RASTA-PLP features. The CFCC features consistently perform much better than PLP. Under white noise, the CFCC features are significantly better than RASTA-PLP, while under car and babble noise, the CFCC features provide similar performances to RASTA-PLP.

An Auditory-Based Feature Extraction Algorithm for Robust Speaker Identification Under Mismatched Conditions

In a switched capacitor amplifier circuit of an offset cancellation type, a capacitor is arranged between a reverse input terminal of an operational-transconductance amplifier and a reference voltage. Only in an offset cancelling operation in which a first group of switches are on, the capacitor functions as a load of the amplifier. The capacitor hence does not exert any influence upon transfer of charge. With provision of the circuit, the phenomenon of oscillation is suppressed in the operation to cancel the offset voltage.

Switched capacitor amplifier circuit

The high cost of capital equipment for production testing coupled with the time that an analog circuit spends on a tester has made it imperative to minimize average chip testing time during production. Testing time can be reduced by decreasing the number of tests that need to be performed on a circuit and by optimizing the order of the tests. This can be done by studying performance data for a sample of chips or using simulation data. The advantage of simulation data is that a large number of circuits do not have to be nonoptimally tested in order to generate the data set. Generating simulation data for very large scale integration (VLSI) analog circuits has been considered to be very difficult because of the computational cost of simulating a large system, the very large number of random variables needed to model the manufacturing process, and the need to model and simulate not only random parameter variations but also spot defects. These problems are overcome by decomposing a circuit into several blocks, which are linked together by a behavioral model of the system. In order for this to work, the blocks must not depend on a large set of significant random variables, and the blocks should not be tightly coupled. In this paper we demonstrate our statistical simulation methodology for a VLSI analog circuit. The proposed approach to defect simulation is applied to a parallel filter bank which has a total of 32 channels, is composed of 67 blocks, and has over 4040 transistors and 750 capacitors. Simulation results are used to optimize the test set for this circuit, by showing that the frequency response tests at many frequencies are redundant.

Optimal testing of VLSI analog circuits

A general scheme for the VLSI implementations of auditory wavelet transforms is proposed using switched-capacitor (SC) circuits. SC circuits are well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by both the capacitor ratios and the clock frequency. The hardware implementations are made possible by several new circuit designs. Specifically, extremely area-efficient designs are presented to implement very large time-constant filters used to process speech and other acoustic signals. The designs employ a charge differencing technique to reduce significantly the capacitance spread ratios needed in the filter banks. Also, a parasitic-insensitive sum-gain amplifier is designed which samples several inputs at the same phase. The proposed circuits have been fabricated using a 2 /spl mu/m CMOS n-well process with double polysilicon and double metal. In addition, a 32-channel prototype filter bank (each channel is a 6th order transfer function), covering a frequency range from 0.2 to 6.4 kHz which includes 36 biquads, 32 sum-gain amplifiers and a preemphasis highpass filter, is implemented on a 4.6/spl times/6.8 mm/sup 2/ die. The IC measurement results of the proposed circuits and the filter bank show the advantages of such new designs. >

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Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits

A parallel dilating-filters switched-capacitor filter bank is described in simulation of the cochlea. Area-saving is achieved by filter-sharing, effective sum-gain amplifier designs, and using area efficient nth-order filter designs, and in particular using a biquadratic filter design using charge-differencing. The structure is easily expandable to include more channels by extending with additional filters and output amplifiers, or by using several chips with different sampling frequencies in parallel connection. An offset-compensated area-efficient switched-capacitor sum-gain amplifier circuit design is described and can be used in the filter bank.

Cochlear filter bank with switched-capacitor circuits

Recent physiological research has shown that synchronization of oscillatory responses in striate cortex may code for relationships between visual features of objects. A VLSI circuit has been designed to provide rapid phase-locking synchronization of multiple oscillators to allow for further exploration of this neural mechanism. By exploiting the intrinsic random transistor mismatch of devices operated in subthreshold, large groups of phase-locked oscillators can be readily partitioned into smaller phase-locked groups. A multiple target tracker for binary images is described utilizing this phase-locking architecture. A VLSI chip has been fabricated and tested to verify the architecture. The chip employs Pulse Amplitude Modulation (PAM) to encode the output at the periphery of the system.

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VLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems

Discusses an architecture for a multiple-target tracking system. This is based on known principles of organization and function in biological systems; local and global aggregation, place and temporal coding, asynchronous computation/communication have been adapted for a silicon implementation. The architecture is verified by prototyping and testing individual system components and a one dimensional version of the architecture. >

Thomas G. Edwards

Papers

Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits

Cochlear filter bank with switched-capacitor circuits

VLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems

Analog VLSI neuromorphic processing: case study of a multiple-target-tracking system