A super-peer is a node in a peer-to-peer network that operates both as a server to a set of clients, and as an equal in a network of super-peers. Super-peer networks strike a balance between the efficiency of centralized search, and the autonomy, load balancing and robustness to attacks provided by distributed search. Furthermore, they take advantage of the heterogeneity of capabilities (e.g., bandwidth, processing power) across peers, which recent studies have shown to be enormous. Hence, new and old P2P systems like KaZaA and Gnutella are adopting super-peers in their design. Despite their growing popularity, the behavior of super-peer networks is not well understood. For example, what are the potential drawbacks of super-peer networks? How can super-peers be made more reliable? How many clients should a super-peer take on to maximize efficiency? we examine super-peer networks in detail, gaming an understanding of their fundamental characteristics and performance tradeoffs. We also present practical guidelines and a general procedure for the design of an efficient super-peer network.

Designing an Super-Peer Network

Systems, apparatuses, and methods for providing an account token to an external entity during the lifecycle of a payment transaction. In some embodiments, an external entity may be a merchant computer requesting authorization of a payment message. In other embodiments, the external entity may be a support computer providing a payment processing network or a merchant support functions.

Securing external systems with account token substitution

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive.

Two-wire dimmer switch for low-power loads

Defect and Fault Tolerance in VLSI Systems

Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.

Full-stripe-write protocol for maintaining parity coherency in a write-back distributed redundancy data storage system

A method and a device for correcting errors in a processor having two execution units as well as a corresponding processor, in which registers are provided in which instructions and/or associated information can be stored, the instructions being processed redundantly in both execution units and comparison means being included, and being such that by comparing the instructions and/or the associated information a deviation and thus an error is detected, a division of the registers of the processor into first registers and second registers being provided, the first registers being such that a specifiable state of the processor and contents of the second registers are derivable from them, means for a rollback being included, which are such that at least one instruction and/or the information in the first registers are rolled back and are executed anew and/or restored.

Device and method for correcting errors in a processor having two execution units

In this paper we propose a generic frame for the implementation of a dual-core processor with two modes of operation. One is the safety mode that allows to run the two cores in lock step in a classical master/checker fashion. A clock delay of 1.5 clock cycles between master and checker establishes the temporal redundancy to minimize the potential for common mode faults. The second operation mode allows a parallel execution of different instruction streams on the two cores in a multiprocessor fashion. The possibility to dynamically switch between the two modes allows for an efficient utilization of the duplicated core. We propose an implementation of such a generic frame that can be applied in conjunction with virtually any standard processor core. Also we perform a systematic failure analysis for the safety mode and the mode switching procedure. Experimental fault injection confirms that our reconfigurable architecture indeed provides the same fail safe properties as the classical master/checker architecture.

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A Reconfigurable Generic Dual-Core Architecture

A device for correcting errors in a system having at least two execution units having registers is presented, the registers being designed for recording data. The device has comparison device(s) that are set up such that through a comparison of data that are provided for storage in the registers, a deviation and thus an error may be ascertained. Furthermore, at least one shadow register that is set up such that data concerning the data of the registers may be stored therein, and device(s) are provided for restoring error-free data in at least one register on the basis of the data in the at least one shadow register when an error is detected. This device may be used to improve the safety of a multicore processor.

Device and method for correcting errors in a system having at least two execution units having registers

The invention relates to a method and a device for switching between at least two operating modes (SM, LM) of a processor unit (100, 101) comprising at least two execution units (ALUA, ALUB) for running programs (P1, P2, P3). At least one characteristic (K2) associated with at least the programs (P1, P2, P3) differentiates between the at least two operating modes (SM, LM), and switching between the operating modes is carried out according to the characteristic (K1-K4, KB) such that the processor unit (100, 101) runs the programs (P1, P2, P3) according to the associated operating mode.

Method and device for switching between at least two operating modes of a processor unit

Errors which may be detected by an error detection unit may occur during execution of a computer program which runs on a computer system and includes at least one run-time object. In order to handle a detected error particularly flexibly and to keep the computer system available as much as possible, an error handling routine is selected from a pre-selectable set of error handling routines as a function of an identifier assigned to the run-time object and the selected error handling routine is executed.

Thomas Kottke

Papers

Device and method for correcting errors in a processor having two execution units

A Reconfigurable Generic Dual-Core Architecture

Device and method for correcting errors in a system having at least two execution units having registers

Method and device for switching between at least two operating modes of a processor unit

Method for running a computer program on a computer system