A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

Memory system and data transmission method

According to one embodiment, A nonlinear editing system comprises a video encoder, an audio compressor and an engine unit. The engine unit is adapted to synchronize the video with the first alternate video and to synchronize the audio with the first alternate audio so that, where the scene of the program includes objectionable content, either (i) the video is substituted with the first alternate video, (ii) the audio is substituted with the first alternate audio, or (iii) both the video and the audio are substituted with the first alternate video and the first alternate audio.

System and method for the creation, synchronization and delivery of alternate content

According to one embodiment, a method for blocking scenes with objectionable content comprises receiving incoming content, namely a scene of a program. Thereafter, using closed captioning information, a determination is made if the scene of the program includes objectionable content, and if so, blocking the scene from being displayed.

Parental control of displayed content using closed captioning

A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift

An outdoor umbrella includes a supporting frame, an awning frame and an audio system. The awning frame includes a functional umbrella hub suspendedly supported by the supporting frame, a plurality of awning frames radially and outwardly extended from the functional umbrella hub, and an awning supported by the awning arms to define a shading area under the awning, wherein the functional umbrella hub has a speaker compartment and an audio outlet. The audio system, as a built-in sound system includes a control panel supported at the supporting frame for inputting an audio signal, and a speaker unit. The speaker unit is supported within the speaker compartment of the functional umbrella hub to align with the audio outlet, wherein when the audio signal is input at the control panel, the audio signal is transmitted to the speaker unit for generating an audio sound as an additional function for the outdoor umbrella.

Outdoor umbrella with audio system

A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Deterministic communication in a clocked system and method therefor

An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Method and apparatus for skewing data with respect to command on a DDR interface

A clock distribution and control system ( 10 ) includes one counter ( 30 ) in a clock generation domain and another counter ( 40 ) in a phase-delayed clock domain. The phase-delayed domain counter ( 40 ) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Thomas L. Thomas

Papers

Deterministic communication in a clocked system and method therefor

Method and apparatus for skewing data with respect to command on a DDR interface

System and method for deterministic communication across clock domains