Patent
Deterministic communication in a clocked system and method therefor
Thomas L. Thomas,Daniel W. Knox +1 more
TLDR
In this paper, the phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system, which is used to insure that communication between logic in the clock generation clock domain and Logic in the phasedelayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.Abstract:
A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.read more
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Patent
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Patent
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PatentDOI
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TL;DR: In this paper, a delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.
References
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Patent
Method and apparatus for synchronizing clock distribution of a data processing system
Abstract: This invention discloses a novel design to solve the clock skew problems in a data processing system by using PLL circuitry inside a memory controller in combination with an adjustable delay element to provide a write clock signal, a read clock signal, and a memory clock signal for triggering the write data buffer and the read buffer of the memory controller, and the memory module respectively. The memory clock signal has a phase lead relative to the read clock signal and a phase lag relative to the write clock signal. The phase lead and the phase lag compensate for phase differences between clock signals arriving at the read data buffer and the write data buffer of the memory controller, and the memory module respectively due to phase delays resulting from the different paths for transmitting clock signals, thereby synchronizing the clock signals.
Patent
Semiconductor device and timing control circuit
TL;DR: In this article, the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is controlled by comparing the phases of two signals.
Patent
Delay locked loop fine tune
TL;DR: In this paper, the coarse delay is adjusted only when the fine delay is at a minimum or maximum delay of the fine-delay range and an increase or decrease in delay is needed respectively.
Patent
Capture clock generator using master and slave delay locked loops
TL;DR: In this article, a master delay-locked loop (DLL) and a slave DLL were used to capture a data signal and the master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal.
Patent
Delay locked loop
TL;DR: In this paper, a delay-locked loop based clocking circuit includes a lead delay line followed by a period delay line and an analog delay control input, and a selected tap of the period line, sometimes called a virtual zero-degree tap, is fed back and phase-compared with the input clock signal.