This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1". If the difference is less than zero, then the next quotient bit is "0". The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0". Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR

An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2 M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2 M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

Iterative division apparatus, system and method forming plural quotient bits per iteration

A data processing apparatus iteratively forms quotient, includes data registers ( 200 ) for storing various initial and intermediate quantities, a multiplexer ( 215 ) for selecting data from one of two data registers, a barrel rotator ( 235 ) and an arithmetic logic unit ( 230 ). A first register ( 200 a ) stores the numerator, which is left shifted each iteration. A second register ( 200 c ) stores the difference formed by the prior trial subtractions. A status register ( 210 ) set by the prior arithmetic logic unit ( 230 ) result controls the selection made by the multiplexer ( 215 ). A barrel rotator ( 235 ) rotates the data selected by multiplexer ( 215 ). The arithmetic logic unit ( 230 ) subtracts the divisor from the rotated quantity this result controls the iterative division process. If the difference is less than zero, then the rotated data is selected and the quotient bit is “0”. Otherwise, the prior difference is selected and the quotient bit is “1”. In the preferred embodiment, the numerator is split between two registers. The trial difference involves only the most significant bits of the numerator. In the preferred embodiment, the inverse of the divisor is stored and the difference is formed by adding the inverse of the divisor. The division processing repeats until the quotient is completely formed and loop logic controls the number of iterations. Also, the data processing apparatus is embodied as at least one digital image/graphics processor ( 71, 72, 73, 74 ) as a part of a multiprocessor ( 100 ) formed in a single integrated circuit.

Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder

A multiply and divide circuit having full bit level pipeline capability uses an array of bit level carry-save adders with each carry-save bit adder having a corresponding absolute value bit circuit. In one or two's complement notation, the carry-save adders subtract the binary values supplied thereto and generate an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary numbers supplied thereto. In one mode of operation, the circuit can be used to perform division. In another mode of operation, the circuit can be used to perform multiply and accumulate operation, again with bit level pipeline capability.

Multiply and divide circuit

A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by twos complement representation. A selector, responding to values of a quotient digit at respective time points during the execution of division, converts the divisor into any of the same value, inverted value or "0" for outputting. An adder adds (subtracts) a partial remainder and 1 or 0. A quotient digit deciding circuit decides the next quotient digit from the quotient digits at respective time points during the execution of division, and a portion of the partial remainder obtained by the adder. The number of transistors constituting an actual circuit can be reduced by using a redundant signal digit (RSD) representation in the same way as the prior art and simplifying tables for deciding the quotient digit.

Divider and microcomputer including the same

A method and apparatus for performing division which calculates a quotient from a dividend and a divisor by using recursive subtraction operations without using carry propagation for each subtraction operation. The apparatus contains a circuit (16) for generating a plurality of quotient digits from the divisor and the dividend. The apparatus also contains a circuit (18, 20) for generating the quotient from the quotient digits.

Thomas Lang

Papers

Method and apparatus for performing division