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Patent

Method and apparatus for performing division

TLDR
In this article, a method and apparatus for performing division which calculates a quotient from a dividend and a divisor by using recursive subtraction operations without using carry propagation for each subtraction operation is presented.
Abstract
A method and apparatus for performing division which calculates a quotient from a dividend and a divisor by using recursive subtraction operations without using carry propagation for each subtraction operation. The apparatus contains a circuit (16) for generating a plurality of quotient digits from the divisor and the dividend. The apparatus also contains a circuit (18, 20) for generating the quotient from the quotient digits.

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Citations
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Patent

Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR

TL;DR: In this article, an iterative technique for division is presented, where each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator.
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Iterative division apparatus, system and method forming plural quotient bits per iteration

TL;DR: In this article, the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.
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Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder

TL;DR: In this paper, a data processing apparatus iteratively forms quotient, including data registers (200 ) for storing various initial and intermediate quantities, a multiplexer ( 215 ) for selecting data from one of two data registers, a barrel rotator ( 235 ) and an arithmetic logic unit ( 230 ).
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Multiply and divide circuit

TL;DR: In this paper, a multiply and divide circuit with full bit level pipeline capability using an array of bit level carry-save adders with each carry save bit adder having a corresponding absolute value bit circuit.
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Divider and microcomputer including the same

TL;DR: A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by two-two complement representation is presented in this paper.
References
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Proceedings ArticleDOI

Compatible hardware for division and square root

TL;DR: Hardware for radix four division and radix two square root is shared in a processor designed to implement the proposed IEEE floating-point standard and obtains the correctly rounded result in about two division times using small extensions to the division hardware.
Patent

Method and apparatus for division using interpolation approximation

TL;DR: In this paper, the divisor and dividend are normalized in a normalization circuit, and the approximate reciprocal divisors read out from the table unit are changed into an interpolation approximation circuit, in accordance with a plurality of bits following the high-order bits and the difference.
Journal ArticleDOI

A Class of Binary Divisions Yielding Minimally Represented Quotients

TL;DR: The method in which partial remainders are always normalized is of particular interest; it yields quotients represented with a minimal number of nonzero digits for all divisors D in the range ?
Patent

Divider using carry save adder with nonperforming lookahead

TL;DR: In this paper, a carry save adder (CSA) is adapted for use in dividing operations by providing it with a lookahead capability whereby it accurately predicts whether or not each of the proposed complemental subtractions in a division process could be successfully performed if actually attempted, and actually performs only those subtractions that will not result in overdrafts.
Patent

Apparatus for generating the inverse of binary numbers

TL;DR: In this paper, a plurality of registers, a comparator subtractor and a clock circuit are used in combination to modify a long division operation to generate the desired inverse number expeditiously.