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Thomas Moscibroda

Researcher at Microsoft

Publications -  237
Citations -  14097

Thomas Moscibroda is an academic researcher from Microsoft. The author has contributed to research in topics: Wireless network & Scheduling (computing). The author has an hindex of 62, co-authored 234 publications receiving 13376 citations. Previous affiliations of Thomas Moscibroda include École Polytechnique Fédérale de Lausanne & ETH Zurich.

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Proceedings ArticleDOI

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

TL;DR: This paper proposes a new memory access scheduler, called the Stall-Time Fair Memory scheduler (STFM), that provides quality of service to different threads sharing the DRAM memory system and shows that STFM significantly reduces the unfairness in theDRAM system while also improving system throughput on a wide variety of workloads and systems.
Journal ArticleDOI

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

TL;DR: A parallelism-aware batch scheduler that seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities, and is also simpler to implement than STFM.
Proceedings ArticleDOI

White space networking with wi-fi like connectivity

TL;DR: This work presents the design and implementation of Net7, the first Wi-Fi like system constructed on top of UHF white spaces, which incorporates a new adaptive spectrum assignment algorithm to handle spectrum variation and fragmentation, and proposes a low overhead protocol to handle temporal variation.
Proceedings ArticleDOI

Flikker: saving DRAM refresh-power through critical data partitioning

TL;DR: Flikker exposes and leverages an interesting trade-off between energy consumption and hardware correctness, and shows that many applications are naturally tolerant to errors in the non-critical data, and in the vast majority of cases, the errors have little or no impact on the application's final outcome.
Proceedings ArticleDOI

A case for bufferless routing in on-chip networks

TL;DR: A case is made for a new approach to designing on-chip interconnection networks that eliminates the need for buffers for routing or flow control and new algorithms for routing without using buffers in router input/output ports are described.