/pdf/scalable-molecular-dynamics-with-namd-3j7xyc70g4.pdf

Scalable Molecular Dynamics with NAMD

Author(s): Asanovic, K; Bodik, R; Catanzaro, B; Gebis, J; Husbands, P; Keutzer, K; Patterson, D; Plishker, W; Shalf, J; Williams, SW | Abstract: The recent switch to parallel microprocessors is a milestone in the history of computing. Industry has laid out a roadmap for multicore designs that preserves the programming paradigm of the past via binary compatibility and cache coherence. Conventional wisdom is now to double the number of cores on a chip with each silicon generation. A multidisciplinary group of Berkeley researchers met nearly two years to discuss this change. Our view is that this evolutionary approach to parallel hardware and software may work from 2 or 8 processor systems, but is likely to face diminishing returns as 16 and 32 processor systems are realized, just as returns fell with greater instruction-level parallelism. We believe that much can be learned by examining the success of parallelism at the extremes of the computing spectrum, namely embedded computing and high performance computing. This led us to frame the parallel landscape with seven questions, and to recommend the following: • The overarching goal should be to make it easy to write programs that execute efficiently on highly parallel computing systems • The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS per development dollar. • Instead of traditional benchmarks, use 13 “Dwarfs” to design and evaluate parallel programming models and architectures. (A dwarf is an algorithmic method that captures a pattern of computation and communication.) • “Autotuners” should play a larger role than conventional compilers in translating parallel programs. • To maximize programmer productivity, future programming models must be more human-centric than the conventional focus on hardware or applications. • To be successful, programming models should be independent of the number of processors. • To maximize application efficiency, programming models should support a wide range of data types and successful models of parallelism: task-level parallelism, word-level parallelism, and bit-level parallelism. 1 The Landscape of Parallel Computing Research: A View From Berkeley • Architects should not include features that significantly affect performance or energy if programmers cannot accurately measure their impact via performance counters and energy counters. • Traditional operating systems will be deconstructed and operating system functionality will be orchestrated using libraries and virtual machines. • To explore the design space rapidly, use system emulators based on Field Programmable Gate Arrays (FPGAs) that are highly scalable and low cost. Since real world applications are naturally parallel and hardware is naturally parallel, what we need is a programming model, system software, and a supporting architecture that are naturally parallel. Researchers have the rare opportunity to re-invent these cornerstones of computing, provided they simplify the efficient programming of highly parallel systems.

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The Landscape of Parallel Computing Research: A View from Berkeley

ABSTRA C T We simulate the assembly of a massive rich cluster and the formation of its constituent galaxies in a flat, low-density universe. Our most accurate model follows the collapse, the star formation history and the orbital motion of all galaxies more luminous than the Fornax dwarf spheroidal, while dark halo structure is tracked consistently throughout the cluster for all galaxies more luminous than the SMC. Within its virial radius this model contains about 2 10 7 dark matter particles and almost 5000 distinct dynamically resolved galaxies. Simulations of this same cluster at a variety of resolutions allow us to check explicitly for numerical convergence both of the dark matter structures produced by our new parallel N-body and substructure identification codes, and of the galaxy populations produced by the phenomenological models we use to follow cooling, star formation, feedback and stellar aging. This baryonic modelling is tuned so that our simulations reproduce the observed properties of isolated spirals outside clusters. Without further parameter adjustment our simulations then produce a luminosity function, a mass-to-light ratio, luminosity, number and velocity dispersion profiles, and a morphology ‐radius relation which are similar to those observed in real clusters. In particular, since our simulations follow galaxy merging explicitly, we can demonstrate that it accounts quantitatively for the observed cluster population of bulges and elliptical galaxies.

Populating a cluster of galaxies - I. Results at z=0

SUMMARY Since 1984, the Condor project has enabled ordinary users to do extraordinary computing. Today, the project continues to explore the social and technical problems of cooperative computing on scales ranging from the desktop to the world-wide computational Grid. In this paper, we provide the history and philosophy of the Condor project and describe how it has interacted with other projects and evolved along with the field of distributed computing. We outline the core components of the Condor system and describe how the technology of computing must correspond to social structures. Throughout, we reflect on the lessons of experience and chart the course travelled by research ideas as they grow into production systems. Copyright c � 2005 John Wiley & Sons, Ltd.

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Distributed computing in practice: the Condor experience

Ganglia is a scalable distributed monitoring system for high performance computing systems such as clusters and Grids. It is based on a hierarchical design targeted at federations of clusters. It relies on a multicast-based listen/announce protocol to monitor state within clusters and uses a tree of point-to-point connections amongst representative cluster nodes to federate clusters and aggregate their state. It leverages widely used technologies such as XML for data representation, XDR for compact, portable data transport, and RRDtool for data storage and visualization. It uses carefully engineered data structures and algorithms to achieve very low per-node overheads and high concurrency. The implementation is robust, has been ported to an extensive set of operating systems and processor architectures, and is currently in use on over 500 clusters around the world. This paper presents the design, implementation, and evaluation of Ganglia along with experience gained through real world deployments on systems of widely varying scale, configurations, and target application domains over the last two and a half years.

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The ganglia distributed monitoring system: design, implementation, and experience

Appendix B: UPC Collective Operations Specifications, v1.0

The emergence of semiconductor fabrication technology allowing a tight coupling between high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-in-Memory (PIM) architectures. Recent developments provide powerful parallel processing capabilities on the chip, exploiting the facility to load wide words in single memory accesses and supporting complex address manipulations in the memory. Furthermore, large arrays of PIMs can be arranged into massively parallel architectures. In this paper, we outline the salient features of PIM architectures and describe the design of an object-based programming and execution model centered on the notion of macroservers. While generally adhering to the conventional framework of object-based computation, macroservers provide special support for the efficient control of program execution in a PIM array. This includes features for specifying the distribution and alignment of data in virtual object space, the binding of threads to data, and a future-based synchronization mechanism. We provide a number of motivating examples and give a short overview of implementation considerations.

Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays

The future of Beowulf-class PC clusters for large-scale scientific and engineering applications will be determined by three issues: system scalability; latency tolerant applications development; and software environments and tools. This paper focuses on the first of these, scalability, which is sensitive to aspects of the remaining two. For the studies and findings described, we consider system designs capable of integrating hundreds or thousands of processors.

Scaling of Beowulf-class distributed systems

Continuum computer architecture (CCA) is a non-von Neumann architecture that offers an alternative to conventional structures as digital technology evolves towards nano-scale and the ultimate flat-lining of Moore's law. Coincidentally, it also defines a model of architecture particularly well suited to logic classes that exhibit ultra-high clock rates (> 100 GHz) such as rapid single flux quantum (RSFQ) gates. CCA eliminates the concept of the "CPU" that has dominated computer architecture since its inception more than half a century ago and establishes a new local element that merges the properties of state storage, state transfer, and state operation. A CCA system architecture is a simple multidimensional organization of these elemental blocks and physically may be considered as a new family of cellular computer. But CCA differs dramatically from conventional cellular automata. While both deliver emergent global behavior from the aggregation of local rules and ensuing operation. The CCA emergent behavior is a global general-purpose model of parallel computation, as opposed to simply mimicking some limited phenomenon like heat and mass transfer as do conventional cellular automata. This paper presents the motivation and foundation concepts of CCA and exposes key issues for further work.

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Thomas Sterling

Papers

Appendix B: UPC Collective Operations Specifications, v1.0

Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays

Scaling of Beowulf-class distributed systems

Continuum computer architecture for nano-scale and ultra-high clock rate technologies

Multiprocessor Performance Measurement Using Embedded Instrumentation.