Electromigration is increasingly relevant to the physical design of electronic circuits. It is caused by excessive current density stress in the interconnect. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years. It is therefore an important reliability issue to consider electromigration-related design parameters during physical design. In this talk, we give an introduction to the electromigration problem and its relationship to current density. We then present various physical design constraints that affect electromigration. Finally, we introduce components of an electromigration-aware physical design flow.

introduction to electromigration-aware physical design

The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC designs. It is therefore necessary to consider electromigration-related design parameters as early as possible in the physical design flow. In this tutorial, we first give an introduction into the electromigration problem and its relationship to current density and temperature. Physical design parameters that affect current density are presented next. We then focus on various distinctive methodologies that allow the electromigration problem to be addressed directly during physical design and verification of both analog and digital circuits. We also present and discuss commercial applications of these electromigration-aware methodologies.

Electromigration-aware physical design of integrated circuits

Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.

Current-driven wire planning for electromigration avoidance in analog circuits

Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraints are specified to the critical nets with monotonic current/signal paths to reduce parasitic impacts. The current-density constraints are usually specified on the nets with variable wire widths to avoid the IR-drop and electromigration problems. In this paper, we propose the first work to simultaneously consider current-flow and current-density constraints while placing and routing the analog circuits with minimized chip area, routed wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an enhanced B*-tree representation to simultaneously model modules and interconnects for an analog circuit. Then a simultaneous placement and routing algorithm is presented to generate a layout while satisfying the current-flow and current-density constraints with minimized chip area, routed wire-length, bend numbers, via counts, and coupling noise. Experimental results show that our approach can obtain better layout results and satisfy all specified constraints while optimizing circuit performance.

Simultaneous analog placement and routing with current flow and current density considerations

A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.

Automatic routing system with variable width interconnect

We present a new methodology for current driven routing and layout verification for analog applications used to avoid defects due to electromigration.The methodology presented uses a commercial simulator to calculate the current flow at all terminals of the analog circuit. Afterwards maximum currents per terminal are extracted and used as guidance for the Current Driven Router (CDR) which is capable of routing analog multiterminal signal nets with current driven wire widths.The Current Density Simulator (CDS) is used to compute and verify current densities in layouts that were generated using a 'standard' routing methodology.

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A current driven routing and verification methodology for analog applications

We present the single layer router CDR (Current Driven Router) capable of routing analog multiterminal signal nets with current driven wire widths. The widths used during routing are determined by current properties per terminal gained by simulation or manually specified by circuit designers. The algorithm presented computes a Steiner tree layout satisfying all specified current constraints while obeying the maximum allowed current densities on all connections. CDR calculates the Steiner tree topology, computes the unknown currents of wires connecting two Steiner points and generates the final Steiner tree layout in a single step thus eliminating the need for a separate layout post-processing step common to power and ground routing algorithms. CDR uses a connection graph for layout representation and applies an advanced minimum detour algorithm in combination with a modified 'three-point steinerization' heuristic for Steiner tree based layout construction.

Single step current driven routing of multiterminal signal nets for analog applications

Summary form only given. We present a new AnalogRouter, specifically developed to address the problems of current densities and electromigration in the routing of multi-terminal, non-planar signal nets in analog circuits. The contributions of our work are: a new current characterization method based on current vectors attached to each terminal; current-driven Steiner tree generation which effectively determines all branch currents prior to detailed routing; and a run-time and memory efficient detailed routing strategy which addresses all features of current-driven circuits, particularly varying wire widths.

/pdf/analogrouter-a-new-approach-of-current-driven-routing-for-3db9thv683.pdf

Thorsten Adler

Papers

A current driven routing and verification methodology for analog applications

Single step current driven routing of multiterminal signal nets for analog applications

AnalogRouter: a new approach of current-driven routing for analog circuits