Analysis of Charged Device Model (CDM) current waveforms on multiple package options / styles shows significant variation with package size / pin count, package physical characteristics and pin location. Die-level CDM analysis shows much higher CDM peak current compared to their packaged counterparts. Thus, package-level CDM results cannot be substituted for die-level CDM results.

http://ieeexplore.ieee.org/iel5/5327110/5340092/05340129.pdf

CDM ESD current characterization — Package variability effects and comparison to die-level CDM

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulse - rise times and -widths. The switching of oxide behavior pre- and post- breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during pulsed stress-method are evaluated using the following two procedures: 1) by adding up the total pulsed stress time, and 2) by extrapolation of the pulsed stress time to a constant voltage stress (CVS)-type measurements. It is shown that the latter method allows for a better comparison of identical oxides TDDB under various stress conditions. A methodology to characterize gate oxide breakdown using a single pulse is finally discussed. This is important to assess the gate-oxide failure condition during a charged device model (CDM)-type electrostatic discharge (ESD).

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

A leading cause of device failure under electrostatic discharge stress conditions is thermal failure. This failure occurs as a result of excessive energy dissipation which raises the temperature of the device to a critical breaking level. To predict such a physical failure at circuit level, a compact model compatible with circuit simulators is proposed. The model is derived from the fundamental heat transfer equations and is shown to accurately predict thermal failure for arbitrary electrical stress waveforms.

Compact Thermal Failure Model for Devices Subject to Electrostatic Discharge Stresses

A low-leakage, low triggering polysilicon bounded SCR design is introduced for on-chip electrostatic discharge (ESD) protection in CMOS applications. The advantages of replacing the shallow trench isolation (STI) with a polysilicon gate in the device formation are discussed. The device response to fast transients, emulating ESD CDM-type events, is discussed through VFTLP measurements. The low-leakage characteristics of the SCR clamp are also demonstrated via high temperature measurements.

A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process

This paper gives solutions to the differential equations of the FICDM tester. Data and theory show that the peak current for FICDM tests increases as the DUT capacitance increases, but approaches a maximum that is a function of the tester field plate capacitance and becomes rather independent of the DUT capacitance.

Effect of large device capacitance on FICDM peak current

A flow and a CAD tool for the simulation of the ESD CDM classification test event in SPICE is described. The methodology consists of deconstructing the CDM test into its relevant components. The modeling and calibration of each component is shown to be essential in the development of a generic simulation approach predicting CDM pass and fail levels. The successful implementation of the flow is demonstrated with a real circuit design example.

http://ieeexplore.ieee.org/iel5/6034620/6045562/06045585.pdf

CDM event simulation in SPICE: A holistic approach

The modeling of ESD devices, such as MOS transistors, under ESD stress and bias conditions is reviewed A practical macro-modeling approach composed of industry standard BJT and MOS compact models is presented SPICE-type circuit level simulations that uses these models is demonstrated These include examples at both the I/O cell as well as full-chip levels Predicting ESD circuit performance as well as the inherent circuit simulation challenges are discussed

ESD Simulation using Compact Models: from I/O Cell to Full Chip

An ESD SPICE simulation design analysis flow for a diverse design environment is introduced. Since the complexities of today's integrated circuits often make full chip transient simulations impractical and in many cases even impossible, this flow includes the automatic extraction of the relevant devices for a given ESD stress. An additional challenge is posed by the high number of simulations required for a comprehensive ESD analysis. To obtain timely results and cater for all required stress pin combinations, the simulations are run in parallel in a compute farm environment. For small to medium designs, a complete ESD performance assessment is typically available within several hours.

Thorsten Weyl

Papers

Effect of large device capacitance on FICDM peak current

CDM ESD current characterization — Package variability effects and comparison to die-level CDM

CDM event simulation in SPICE: A holistic approach

ESD Simulation using Compact Models: from I/O Cell to Full Chip

ESD event simulation automation using automatic extraction of the relevant portion of a full chip