Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Bi-directional blocking voltage protection devices and methods of forming the same

Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same

A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference The conduction paths may be built into a single structure with dual isolation regions As a result, the protection device enables superior robustness and compact protection solutions for smart power applications

Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals

Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Apparatus and method for protection of precision mixed-signal electronic circuits

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T 1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.

Apparatuses for communication systems transceiver interfaces

This paper gives solutions to the differential equations of the FICDM tester. Data and theory show that the peak current for FICDM tests increases as the DUT capacitance increases, but approaches a maximum that is a function of the tester field plate capacitance and becomes rather independent of the DUT capacitance.

Effect of large device capacitance on FICDM peak current

On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.

On-chip protection for automotive integrated circuits robustness

This article provides an understanding of the transient voltage overshoot physics observed with electro-static discharge (ESD) n-type, p-type, and n-type diffusions (NPN) bipolar devices through the use of calibrated technical computer-aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8-kV IEC61000-4-4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80-V bipolar and complimentary double-diffused metal-oxide semiconductor (BiCDMOS) process platform to protect against a product level 125-V voltage overshoot gate oxide ruptures as measured with a 0.6-ns rise time transmission line pulse (TLP). The fully characterized electrical results for each test overshoot structure with a fixed layout area of $200\,\,\mu \text{m}\,\,\times200\,\,\mu \text{m}$ , are in parallel to NPN ESD cells arranged with two in series and two in parallel ( $200\,\,\mu \text{m}\,\,\times 80\,\,\mu \text{m}$ ) and compared in terms of the current-carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125-V, resulting in a net 0.17 mA $\mu \text{m}^{-{2}}$ . The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7-A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8-kV International Electrotechnical Commission (IEC) ESD performance for this case study.

Designing ESD Protection Devices for Ultrafast Overvoltage Events

An ESD SPICE simulation design analysis flow for a diverse design environment is introduced. Since the complexities of today's integrated circuits often make full chip transient simulations impractical and in many cases even impossible, this flow includes the automatic extraction of the relevant devices for a given ESD stress. An additional challenge is posed by the high number of simulations required for a comprehensive ESD analysis. To obtain timely results and cater for all required stress pin combinations, the simulations are run in parallel in a compute farm environment. For small to medium designs, a complete ESD performance assessment is typically available within several hours.

ESD event simulation automation using automatic extraction of the relevant portion of a full chip

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Dave Clarke

Papers

Effect of large device capacitance on FICDM peak current

On-chip protection for automotive integrated circuits robustness

Designing ESD Protection Devices for Ultrafast Overvoltage Events

ESD event simulation automation using automatic extraction of the relevant portion of a full chip

Electrical overstress detection device