Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

Phd by thesis

We present a user-controllable, general-purpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and inter-task communication. The user may parametrically control the correlations between attributes. Sharing TGFF's parameter settings allows researchers to easily reproduce the examples used by others, regardless of the platform on which TGFF is run.

/pdf/tgff-task-graphs-for-free-3cut2n9zse.pdf

TGFF: task graphs for free

1 Introduction 2 Models and Architectures 3 Specification Languages 4 A Specification Example 5 Translation to VHDL 6 System Partitioning 7 Design Quality Estimation 8 Specification Refinement into Synthesizable Models 9 System-Design Methodology and Environment Appendix: Answering Machine in SpecCharts Bibliography Index

Specification and Design of Embedded Systems

The Wireless Integrated Network Sensor Next Generation (WINS NG) nodes provide distributed network and Internet access to sensors, controls, and processors that are deeply embedded in equipment, facilities, and the environment. The WINS NG network is a new monitoring and control capability for applications in transportation, manufacturing, health care, environmental monitoring, and safety and security. The WINS NG nodes combine microsensor technology, low power distributed signal processing, low power computation, and low power, low cost wireless and/or wired networking capability in a compact system. The WINS NG networks provide sensing, local control, remote reconfigurability, and embedded intelligent systems in structures, materials, and environments.

Apparatus for internetworked wireless integrated network sensors (wins)

Most electronic systems, whether self contained or embedded, have a predominant digital component consisting of a hardware platform which executes software application programs. Hardware/software co-design means meeting system level objectives by exploiting the synergism of hardware and software through their concurrent design. Co-design problems have different flavors according to the application domain, implementation technology and design methodology. Digital hardware design has increasingly more similarities to software design. Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware design. Current integrated circuits can incorporate one (or more) processor core(s) and memory array(s) on a single substrate. These "systems on silicon" exhibit a sizable amount of embedded software, which provides flexibility for product evolution and differentiation purposes. Thus the design of these systems requires designers to be knowledgeable in both hardware and software domains to make good design tradeoffs. The paper introduces various aspects of co-design. We highlight the commonalities and point out the differences in various co-design problems in some application areas. Co-design issues and their relationship to classical system implementation tasks are discussed to help develop a perspective on modern digital system design that relies on computer aided design (CAD) tools and methods.

/pdf/hardware-software-co-design-4yg9c0ruz5.pdf

Hardware/software co-design

Communication synthesis is an essential step in hardware-software co-synthesis: many embedded systems use custom communication topologies and the communication links are often a significant part of the system cost. This paper describes new techniques for the analysis and synthesis of the communication requirements of embedded systems during co-synthesis. Our analysis algorithm derives delay bounds on communication in the system given an allocation of messages to links. This analysis algorithm is used by our synthesis algorithm to choose the required communication links in the system and assign interprocess communication to the links. Experimental results show that our algorithm finds good communication architectures in small amounts of CPU time.

/pdf/communication-synthesis-for-distributed-embedded-systems-3u33gdsosq.pdf

Communication synthesis for distributed embedded systems

From the Publisher:
Hardware-Software Co-Synthesis of Distributed Embedded Systems is the first book to describe techniques for the design of distributed embedded systems, which have arbitrary hardware and software topologies. The book will be of interest to academic researchers for personal libraries and advanced-topic courses in co-design as well as industrial designers who are building high-performance, real-time embedded systems with multiple processors.

Hardware-Software Co-Synthesis of Distributed Embedded Systems

Describes a new, sensitivity-driven algorithm for the co-synthesis of real-time distributed embedded systems. Many embedded computing systems are distributed systems: communicating periodic processes executing on several CPUs/ASICs connected by communication links. We use performance estimates to compute a local sensitivity of the design to process allocation. We propose a priority prediction method to schedule processes. Based on these techniques, we develop a gradient-search algorithm which co-synthesizes heterogeneous distributed systems of arbitrary topology and the associated application software architecture. Experimental results show that our algorithm can find good implementation architectures in small amounts of CPU time.

Sensitivity-driven co-synthesis of distributed embedded systems

This paper presents algorithms for computing separations between events that are constrained to obey prespecified relationships in their relative time of occurrence. The algorithms are useful for interface timing verification, where event separations are checked against timing requirements. The first algorithm computes separations when only linear and max constraints exist. The algorithm must converge to correct maximum separation values in a finite number of steps, or report an inconsistence of the constraints, irrespective of the existence of infinite constraint bounds or infinite event separations. It is conjectured to run in \(O(VE + V^2 {\text{ log }}V)\) time, where V is the number of events, and E is the number of relationships between them. The other algorithms extend the first, and compute event separations in the NP-complete version of the problem where min constraints exist. Experiments demonstrate the algorithms are efficient in practice.

Efficient algorithms for interface timing verification

Embedded computer systems are characterized by the presence of one or more processors running application specific software. A large number of these systems must satisfy performance constraints in addition to cost constraints. Because embedded systems are constructed from large, complex components — CPUs and ASICs — we need new techniques to analyze the performance of these components as well as their compositions. Since the performance analysis of ASICs is considered to be a well studied problem, the main challenges in performance analysis of embedded system are in the area of software performance analysis and analysis of concurrent components. Here the research can be broadly classified into two areas. Program analysis methods consider the behavior of a single process on a given processor and attempt to determine bounds on the execution time of the process. This task is made complicated for modern CPUs by the presence of relatively non-deterministic features such as caches and instruction pipelines which make the execution time of one instruction depend on both the recent and distant history of the executed instruction trace. System analysis methods study the performance of a network of machines—either CPUs or ASICs—which execute a set of processes. Even if we know the execution time of each process in isolation, we must consider conflicts in allocation of processes to processing elements and the scheduling of events on the processing elements and communication channels.

https://link.springer.com/content/pdf/10.1007%2F978-94-009-0187-2_3.pdf

Ti-Yen Yen

Papers

Communication synthesis for distributed embedded systems

Hardware-Software Co-Synthesis of Distributed Embedded Systems

Sensitivity-driven co-synthesis of distributed embedded systems

Efficient algorithms for interface timing verification

Performance Analysis of Embedded Systems