Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

/pdf/differential-power-analysis-4t7fjmuc7b.pdf

Differential Power Analysis

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

http://users.ece.gatech.edu/limsk/www/pdfs/integration97.pdf

Performance optimization of VLSI interconnect layout

In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner trees or RATS-trees, providing a smooth trade-off among signal delay, waveform, and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.

/pdf/interconnect-design-for-deep-submicron-ics-1wpzzxlew8.pdf

Interconnect design for deep submicron ICs

In this paper, we introduce a general method of interconnect simulation based on distributed circuits. The algorithm is very efficient and consists of two main steps. In the first step, each distributed line is modeled by a finite order system with passivity preservation and multipoint moment matching of its input admittance/impedance matrix. In the second step, an Arnoldi-based congruence transform is applied to the network to form its reduced order model. The main feature of the algorithm is in its first step, where a passive multipoint moment matching model of a distributed line can be generated without any discretization of the line. We provide an integrated-congruence transform which can be directly applied to the partial differential equations of a distributed line and generate a passive finite order system as its model. We also provide an algorithm based on the L/sup 2/ Hilbert space theory so that exact moment matching at multiple points can be obtained, We demonstrate the accuracy of our method with examples and show the advantage of ours over conventional ones based on lumped circuit models.

Passive multipoint moment matching model order reduction algorithm on multiport distributed interconnect networks

This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms Experiment results are given to demonstrate the effectiveness of the two algorithms

Performance-Driven Steiner Tree Algorithms for Global Routing

Previous approaches for crosstalk synthesis often fail to achieve satisfactory results due to limited routing flexibility. Furthermore, the risk tolerance bounds partitioning problem critical for constrained optimization has not been adequately addressed. This paper presents the first approach for crosstalk risk estimation and reduction at the global (instead of detailed) routing level. It quantitatively defines and estimates the risk of each routing region using a graph-based optimization approach and globally adjusts routes of nets for risk reduction. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the crosstalk situation of the chip. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising.

/pdf/post-global-routing-crosstalk-risk-estimation-and-reduction-5b0gqis2zo.pdf

Post global routing crosstalk risk estimation and reduction

This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the maximum rising delay by over 60% with small penalty in routing area. Besides delay optimization, the final solution eliminates the over-shoot of response waveform and is robust under parameter variations.

A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies

In this paper, we propose an efficient timing-driven global router, TIGER, for gate array and standard cell layout design. Unlike other conventional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to minimize the maximum channel density for gate arrays or the total track number for standard cells, as well as to satisfy the timing constraints in TIGER. The timing-driven global routing problem is formulated as a multiterminal, multicommodity network flow problem with integer flows under additional timing constraints. Two novel performance-driven Steiner tree algorithms are proposed to generate the initial global routing trees. A critical-path-based timing analysis method is used to guarantee the satisfaction of timing constraints. Experimental results based on MCNC (ISCAS) benchmarks show that TIGER can obtain better results than or comparable results with TimberWolf 5.6.

TIGER: an efficient timing-driven global router for gate array and standard cell layout design

Most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. This paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. Unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. During optimization, the topology of the net is kept routable. Experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.

/pdf/post-routing-performance-optimization-via-multi-link-ma35hu01es.pdf

Tianxiong Xue

Papers

Performance-Driven Steiner Tree Algorithms for Global Routing

Post global routing crosstalk risk estimation and reduction

A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies

TIGER: an efficient timing-driven global router for gate array and standard cell layout design

Post routing performance optimization via multi-link insertion and non-uniform wiresizing