Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study

A review on emerging negative capacitance field effect transistor for low power electronics

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer (<inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}})$ </tex-math></inline-formula> is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula> on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula> yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula> is increased. Depending on the attributes of the underlying transistor, increasing <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula> beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula> on the circuit energy–delay. Our analysis shows that for high <inline-formula> <tex-math notation="LaTeX">$T_{\textsf {FE}}$ </tex-math></inline-formula>, the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay.

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DEVICE CIRCUIT ANALYSIS OF FERROELECTRIC FETs FOR LOW POWER LOGIC & MEMORIES

Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

Effect of different capacitance matching on negative capacitance FDSOI transistors

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

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Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

This paper presents a detailed investigation of the timing variation due to random channel dopants for 22nm Complementary-Metal-Oxide-Semiconductor (CMOS) inverter. Consequently, the timing parameters such as propagation delay, rise time, fall time, high-to-low transition, low-to-high transition and overshooting time and their variations have been extracted and estimated with channel dopants fluctuations. Furthermore, the influence of load capacitance and power supply voltage on timing characteristic also has been studied. This investigation was performed by HSPICE simulation with a high accuracy, which is important for yield improvement and the optimization of CMOS circuit design.

Effect of Random Channel Dopants on Timing Variation for Nanometer CMOS Inverters

In this study, we compared the timing and its random dopant fluctuation (RDF)-induced variations in nanometre conventional and negative-capacitance CMOS (NC-CMOS) inverters. The authors found that the transition delay in the NC-CMOS inverter exhibits a strongly dependence on the viscosity coefficient (ρ) of the ferroelectric (FE). Only NC-CMOS using sufficiently low ρ with smaller response time to baseline CMOS can be considered as a low-power device with a smaller propagation delay. Due to the steeper transient subthreshold swing and lower threshold voltage (V th), the timing parameters, e.g. rise time, fall time, high-to-low transition, low-to-high transition, and propagation delay were all reduced. Furthermore, RDF-induced timing variations can be effectively suppressed by the negative capacitance effect provided by the FE capacitor and the fluctuation of static DC power also drops, and this immunity to RDF-induced timing variations increases with increasing FE thickness (T FE). Our analysis was verified by technology-aided design simulation and can provide useful insights into future studies of low-power CMOS digital circuits.

Tianyu Yu

Papers

Effect of different capacitance matching on negative capacitance FDSOI transistors

Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

Effect of Random Channel Dopants on Timing Variation for Nanometer CMOS Inverters

Performance improvement of timing and power variations due to random dopant fluctuation in negative-capacitance CMOS inverters