Showing papers in "Iet Circuits Devices & Systems in 2020"

Design and development of symmetrical super-lift DC–AC converter using firefly algorithm for solar-photovoltaic applications

Abstract: The super-lift technique is an exceptional contribution to DC-DC conversion technology. A replacement approach of symmetrical super-lift multilevel inverter (SLMLI) DC/AC technology is proposed with a reduced number of elements compared with the traditional multilevel inverter. In this method, the firefly algorithm conveys a leading task for the SLMLI topology for solar-photovoltaic applications. It generates low distortion output and consumes the harmonic band of the fast Fourier transform framework by the employment of the proposed algorithm. The simulation circuit for 15 levels output uses single switch super-lift inverter feed with different kinds of load (R, RL and RLE) conditions. The power quality is improved in SLMLI with minimised harmonics underneath the various modulation indices while varied from 0.1 up to 0.8. The circuit is designed in a field-programmable gate array, which includes the firefly rule to help the multilevel output, to reduce the lower order harmonics and to find the best switching angle. As a result, the minimum total harmonic distortion from the simulation and hardware circuit is achieved. Due to the absence of bulky switches, inductor and filter elements expose the effectiveness of the proposed system.

Design of ternary logic gates and circuits using GNRFETs

Abstract: In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Physical unclonable function: architectures, applications and challenges for dependable security

Abstract: Physical unclonable function (PUF) is hardware-specific security primitive for providing cryptographic functionalities that are applicable for secure communication among the embedded devices. The physical structure of PUF is considered to be easy to manufacture but hard or impossible to replicate due to variations in its manufacturing process. However, a large community of analytics believes hardware-based PUF has paved the way for its realisation in providing dependable security. In this study, the authors have thoroughly explored the architecture, applications, requirements, and challenges of PUF that provide security solutions. For presenting the literature, they have designed a taxonomy where PUFs are divided under two main categories, including non-silicon and silicon-based PUF. Currently, there is no comprehensive survey that highlights the comparison and usability of memory-based and analogue/mixed-signal based PUF that are considered to be suitable as compared to counterparts. In a similar vein, they have presented the network-specific application scenarios in wireless sensor network, wireless body area network and Internet of Things and then identified the strong, weak and controlled PUF in a categorical manner. Moreover, they have presented a number of prospective limitations that are identified in PUF structures and then identified the open research challenges to meet the desired security levels.

Reliable write assist low power SRAM cell for wireless sensor network applications

Abstract: In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Self-refreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product ( R PDP ) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product ( W PDP ) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

Design and applications of interval observers for uncertain dynamical systems

Abstract: Interval observer design and related techniques have been researched and applied in many engineering fields and continue to be an active research area in the estimation and control society for the last two decades. An Interval observer is a special class of observers that generates a bounded interval vector for the real state vector in a guaranteed way under the assumption that the uncertainties are unknown but bounded. Some of the basic concepts and the main developments in the designs and applications of interval observer for continuous-time, discrete-time (linear and non-linear), fuzzy and switched systems are reviewed in this work. It also provides a brief discussion of the main approaches in this area with clear descriptions of their structures and future directions.

New mixed-mode second-generation voltage conveyor based first-order all-pass filter

Abstract: A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 μm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters.

Split gated silicon nanotube FET for bio-sensing applications

Abstract: A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (I ON) and the threshold voltage (V th) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive simulations have been done using the SILVACO ATLAS. Sensitivity analysis has been carried out by considering half-filled and full-filled nanogaps with the neutral or charged biomolecules inside the cavity. Significant sensitivity and excellent reduction in short-channel effects has been observed in proposed biosensor.

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Abstract: Security and privacy of the Internet of Things (IoT) systems are critical challenges in many data-sensitive applications. The IoT systems are constrained in terms of execution time, flexibility and computational resources. In recent years, many encryption algorithms have been proposed to provide the security of IoT communication. In this study, flexible and high-throughput hardware structures of the PRESENT, SIMON, and LED lightweight block ciphers are presented for IoT applications. The proposed flexible structures can perform various configurations of these block ciphers to support variable key sizes. For example, the PRESENT, SIMON, and LED ciphers support key sizes (80, 128 bits), (96, 144, 128, 192, and 256 bits), and (64, 128 bits), respectively. Therefore, these architectures provide versatile implementations that enable adaptive security level using a variable key size. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. In the PRESENT and LED ciphers, the S-boxes are implemented based on area-optimised logic circuits. The implementation results of proposed flexible architectures are achieved in 180 nm CMOS technology. Area, throughput and throughput/area of the proposed structures have improved compared to other related works.

Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction

Abstract: Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal–oxide–semiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors propose a heterojunction doping less tunnel field-effect transistor with an asymmetric double gate (HJ ADG DLTFET). This device employs a low bandgap material at the source region, which increases the BTBT rate at the channel–source interface leading to enhanced drive current while maintaining low off-current. Consequently, an increment of one order for I ON (∼1.5 × 10−5 A/µm) compared to the conventional ADG DLTFET has been provided by this device. Additionally, the comparative analysis of the proposed device and conventional one has been performed to reveal the advantages of the proposed structure in terms of transfer characteristics, transconductance, gate-to-drain capacitance, cut-off frequency, gain–bandwidth product, device efficiency, and transconductance frequency product. Moreover, the effect of gate length and drain voltage variations has been analysed for HJ ADG DLTFET concerning the aforementioned characteristics.

Systematic circuit design and analysis using generalised g m/I D functions of MOS devices

Abstract: The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V - 28 μA reference circuit, and a 7.50 μA/V operational-transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

On-chip tunable Memristor-based flash-ADC converter for artificial intelligence applications

Abstract: This study presents a novel hybrid memristor (MR)-complementary metal–oxide–semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.

Implementation of fast ICA using memristor crossbar arrays for blind image source separations

Abstract: Independent component analysis (ICA) is an unsupervised learning approach for computing the independent components (ICs) from the multivariate signals or data matrix. The ICs are evaluated based on the multiplication of the weight matrix with the multivariate data matrix. This study proposes a novel Pt/Cu:ZnO/Nb:STO memristor crossbar array for the implementation of both ACY ICA and Fast ICA for blind source separation. The data input was applied in the form of pulse width modulated voltages to the crossbar array and the weight of the implemented neural network is stored in the memristor. The output charges from the memristor columns are used to calculate the weight update, which is executed through the voltages kept higher than the memristor Set/Reset voltages (±1.30 V). In order to demonstrate its potential application, the proposed memristor crossbar arrays based fast ICA architecture is employed for image source separation problem. The experimental results demonstrate that the proposed approach is very effective to separate image sources, and also the contrast of the images are improved with an improvement factor in terms of percentage of structural similarity as 67.27% when compared with the software-based implementation of conventional ACY ICA and Fast ICA algorithms.

Wearable technology for infant health monitoring: a survey

Abstract: Continuous health monitoring for an infant is crucial for detecting and preventing several diseases. Recent advancement in wearable technology has given rise to the development of wearable infant health monitoring systems (WIHMSs). These systems provide an edge over conventional infant health monitoring systems which are not only bulky and uncomfortable for the infants but are also limited to the clinical settings. This study reviews some state-of-the-art WIHMS, mentions the advantages, limitations and the challenges faced by such systems. This study, for the first time, contributes an appraisal of research prototypes and commercially available systems for WIHMS, which is the need of the day.

Developed wireless sensor network to supervise the essential parameters in greenhouses for internet of things applications

Abstract: Recently, the wireless sensor networks have rapidly emerged into agriculture and greenhouse because of owing many advantages than the traditional methods. However, some subjects such as cost and power are being brought up as a controversial issue. This study presents a developed wireless sensor network based on a proposed algorithm to improve tomato crop in a greenhouse. The developed sensor nodes, which own low-power consumption and also low-cost, monitor parameters like temperature, humidity, CO, C O 2 and light intensity. The users define the minimum and maximum setpoints for the sensors to make an appropriate condition in the greenhouse. Also, the developed system was equipped with irrigation management that works based on time and date that maintain optimum water in the soil. The obtained results reveal that the amount of the tomato crops increases 30% than traditional methods after benefiting the developed system as well as the greenhouse experiences a decrease in consuming methane gas, water, and electricity as 30, 24 and 10% separately, in comparison to the traditional methods.

Floating memristor and inverse memristor emulation configurations with electronic/resistance controllability

Abstract: This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator is based on two MVDCCs, two grounded resistances and single grounded capacitance. The behaviour of both the circuits can be controlled through applied bias voltage as well as the employed grounded resistances. Both the presented circuits do not employ any external analogue multiplier circuit/IC, which can be considered as the most notable feature of these circuits. This study also describes the mathematical properties of memristor and inverse memristor taking both symmetrical and non-symmetrical models into account. PSPICE simulation tool is used to verify the working of realised emulation circuits using 0.18 μm CMOS process technology. The implementations of realised emulators, employing commercial ICs like AD844, CA3080 and LM13700, have also been presented and validated.

Time-based all-digital time-to-digital converter with pre-skewed bi-directional gated delay line time integrator

Abstract: An all-digital first-order single-bit Δ Σ time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the per-stage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the per-stage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

Memristor-based stateful logic gates for multi-functional logic circuit

Abstract: Memristor-based stateful logic circuits can perform logic operations and logic value storage, which creates an intriguing opportunity for the implementation of an advanced computational architecture. This study proposes a novel memristor-based stateful logic implementation. Specifically, the presented approach is capable of realising two-input or multi-input AND, OR, NAND and NOR operations, and single-input COPY and NOT operations. In each logic gate, non-volatile resistances of memristor are used as input and output states, thus enabling stateful logic operations. Compared with several existing approaches, the proposed method can lead to a multi-functional stateful logic circuit, performing multiple stateful logic operations simultaneously. The effectiveness of the proposed design is demonstrated with the simulation results of MATLAB and SPICE.

Integer-N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Abstract: In this article, a novel design is presented, for an Integer- N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder

Abstract: In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.

Dual-band CPW rectenna for low input power energy harvesting applications

Abstract: A dual-frequency band low input power rectenna is proposed in this study. The rectenna is comprised of a co-planar waveguide (CPW) rectifier integrated with a rectangular split ring antenna loaded by a spiral strip line. A single diode series connection topology is used to miniaturise the losses at low input power. A spiral coil in addition to two short circuit stubs are used as a matching network for maximum power transfer between the antenna and the rectifying circuit. The proposed rectenna operates at low input power with relatively high measured RF-DC conversion efficiency up to 74 % at input power of − 6.5 dBm at the first resonant frequency f 1 = 700 MHz and 70 % at − 4.5 dBm at the second operating frequency f 2 = 1.4 GHz with a resistive load of 1.9 k Ω . The measured rectenna sensitivity (the rectenna ability to receive low power with acceptable conversion efficiency) reaches up to − 20 dBm with a conversion efficiency of 47 and 36 % at f 1 and f 2 , respectively, and a DC output voltage of 0.18 V . The measured efficiency is over 50 % from − 18 to − 3.5 dBm and from − 15 to − 1.5 dBm at f 1 and f 2 , respectively.

Single DDCC− based simulated floating inductors and their applications

Abstract: Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus-type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum number of passive elements. As application examples, second-order current-mode (CM) and voltage-mode low-pass (LP) filters derived from the proposed series lossy SFI are given. Also, a fourth-order CM Butterworth LP filter example is presented as another application. A second-order CM high-pass (HP) filter and an RLC resonant circuit obtained from the proposed parallel lossy SFI are given. All the simulations are achieved via SPICE program. Moreover, some experimental results for the proposed lossy SFIs and CM HP filter are given in order to show the performances.

Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation

Abstract: This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

Multiple cascode flipped active inductor-based tunable bandpass filter for fully integrated RF front-end

Abstract: A multiple cascode flipped active inductor (MCASFAI) is proposed to determine the degrees of freedom in cascode flipped active inductor (CASFAI). The inductance value of CASFAI is dependent on negative transconductor in gyrator network. This finding is in contrast to the finding that has been reported in the literature, on the degrees of freedom in CASFAI. As the transconductance of negative transconductor increases, inductance decreases, and quality factor increases. The MCASFAI proposed in this study is designed to enhance both inductance and quality factor of CASFAIs. Analytical modelling is done to determine the design parameters that affect inductance and quality factor in CASFAI. Verification is done using Cadence Virtuoso in 180 nm process. Bandpass filter based on the proposed MCASFAI is designed to operate at 2.45 GHz centre frequency with a bandwidth of 80 MHz. The designed filter attains a dynamic range of 162 dB-Hz and figure of merit of 153 dB-HZ/mW, which is comparable to the bandpass filter designs reported in the literature.

Ultra-low power low-complexity 3–7.5 GHz IR-UWB transmitter with spectrum tunability

Abstract: An impulse radio ultra-wideband (IR-UWB) transmitter (TX) consuming ultra-low power is presented. The low-complexity topology features control of the power spectral density (PSD) and central frequency for a broad range of applications. The PSD and frequency adjustment are accomplished by employing a tunable pulse generator and an adjustable driver. The IR-UWB TX suitable for on–off keying coding is fabricated in a low-cost 180 nm UMC CMOS technology and occupies the total die area of 0.63 mm2. The measurement results show the transmitter output swing of 320 mVpp (peak-to-peak amplitude) with the pulse duration of 0.6 ns, and the spectrum covering the frequency range from 3 to 7.5 GHz. The total DC power consumption is 1 mW resulting in energy consumption of 5 pJ/pulse at 200 MHz data rate.

Suppression of ambipolarity in tunnel-FETs using gate oxide as parameter: analysis and investigation

Abstract: In this study, the authors present a double-gate tunnel field-effect transistor with dual gate oxide thickness (henceforth referred to as DOT-DGTFET) to suppress ambipolar current conduction (I amb). Conventional n-type DGTFET conducts current for negative V GS also and poses a challenge for circuit design. Conduction current in n-type DGTFET for negative V GS is referred to as ambipolar current (I amb). In the proposed DOT-DGTFET structure, a thin gate oxide of 3 nm is used towards the source–channel junction and a thick gate oxide is used towards the drain–channel junction. Use of thicker gate oxide towards drain–channel junction suppresses I amb significantly while only marginally affecting I ON. Subsequently, the proposed technique for ambipolarity suppression is compared with some of the existing techniques and they observe that DOT-DGTFET suppresses ambipolarity significantly with minimal effect on the ON state current.

3D-IC partitioning method based on genetic algorithm

Abstract: In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing-based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal-aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.

Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications

Abstract: This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f T) and maximum oscillator frequency (f MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.

Design of a voltage-programmed V TH compensating pixel circuit for AMOLED displays using diode-connected a-IGZO TFT

Abstract: This study presents a novel voltage-programmed, amorphous-indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT)-based active-matrix organic light-emitting diode (AMOLED) pixel circuit. The circuit utilises the threshold voltage ( V TH ) sensing ability of a diode-connected transistor to compensate for the spatial as well as the temporal variation of the threshold voltage of the driving transistor and supply a constant current to the OLED. The circuit has been simulated in Cadence Spectre using a-IGZO TFT and OLED simulation program with integrated circuit emphasis (SPICE) models, and the analysis is presented to prove the V TH compensating capability of the proposed circuit. For small currents, about 50 nA, the error is suppressed to <9% whereas for large currents, about 2.5 µA, the error is only 1.05%. This performance has been achieved using only five TFTs and two storage capacitors.

High gain operational amplifier and a comparator with a-IGZO TFTs

Abstract: This study presents a novel high gain operational amplifier (op-amp) and a comparator using n -type all enhancement amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The proposed op-amp employs regulated cascode topology in conjunction with capacitive bootstrap load, which enhances the gain to 159.87% (V/V) as compared to op-amp with bootstrapping load. In addition, common mode feedback is introduced in the circuit which improves the common-mode rejection ratio (CMRR) of the amplifier without hampering the output voltage swing. The proposed op-amp offers a voltage gain of 46.2 dB, phase margin of 67°, CMRR of 51.8 dB, unity gain frequency of 215 kHz and power consumption of 0.22 mW. Furthermore, a novel comparator circuit at a clock frequency of 50 kHz is reported. The power consumption of the circuit is 0.248 mW and it can discriminate a minimum voltage of 50 mV. The performance of the proposed circuits is demonstrated using an analytical model of a-IGZO in Cadence environment with a channel length of 20 µm at a supply voltage of 10 V. Further with the help of the circuits reported in this work, many sensing systems of practical importance can be developed, such as smart packaging and bio-medical wearable devices using flexible electronics.

Parallel architecture of power-of-two multipliers for FPGAS

Abstract: This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.