A practical high-throughput architecture and its implementation for real-time coding of television-quality signals are presented. The architecture is directed toward the implementation of multistage vector quantization (VQ), as the authors' simulation results show that the latter is more suitable for real-time coding. However, the implementation is suitable for both single-stage and multistage VQ. The functional blocks of the VQ encoder system have been designed and implemented in VLSI technology. The VQ encoding scheme designed has an encoding delay of 25 clock cycles and is independent of the codebook size. >

Bit-serial VLSI implementation of vector quantizer for real-time image coding

Image compression by vector quantization: a review focused on codebook generation

In an image coding and decoding device, input digital image signals are divided into blocks of prescribed size, and coding processing is performed to differential signal taken between the input block signal and interframe forcasting signal thereby transmission recording is performed.

Image coding and transmitting apparatus

The implementation of real-time image encoding requires a high and constant throughput rate not achievable by a SISD machine. With a reasonable size codebook and SIMD machine architecture. Vector Quantization algorithm can be implemented in real-time. But, single stage Vector Quantization requires fairly large-size codebook for good quality image encoding. Multi-Stage Vector Quantization with codebooks of moderate size at each stage has been shown to be an alternative viable approach. The bits per pixel rates for TV quality composite color image encoding using Multi-Stage Vector Quantization are reported. The VQ/MSVQ implementation requires two processors, inner product processor and comparator-address generator. The implementation details of the processors and their throughput rate are described.

Bit serial systolic chip set for real-time image coding

Image coding and decoding system

Secure and reliable image transmission is achieved using a representation of video images in digital form and digital communication techniques However, the digital representation results in a large increase in the transmission bandwidth required Hence the need for coding or compression techniques that will reduce the bandwidth required or equivalently the bit-rate involved as much as possible for a given level of reconstructed image quality From Information Theory, we know that it is possible to obtain better performance by coding vectors of picture elements instead of coding the individual pixels Nevertheless, application of Vector Quantizers is limited due to the high computational complexity With curent VLSI technology this can be changed The repetitive nature of VQ error computation and codebook vectors comparison points to us that using special structure such as systolic type architecture, VQ can be VLSI implemented to make real-time applications possible Along with full search VQ, we emphasize on the implementation of multistage VQ which can significantly reduce the computation load due to much smaller codebooks required Examples of processed images are presented to show the validity of such an approach

Tien Tran

Papers

A Systolic Architecture for Real-Time Composite Video Image Coding