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Tim Harris
Researcher at Oracle Corporation
Publications - 178
Citations - 15620
Tim Harris is an academic researcher from Oracle Corporation. The author has contributed to research in topics: Transactional memory & Software transactional memory. The author has an hindex of 44, co-authored 173 publications receiving 15244 citations. Previous affiliations of Tim Harris include Amazon.com & Microsoft.
Papers
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Patent
On-demand code execution in input path of data uploaded to storage service in multiple data portions
TL;DR: In this paper, the authors describe a system and methods for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests.
Transaction processing core for accelerating software transactional memory
Ferad Zyulkyarov,Milos Milovanovic,Osman Unsal,Adrián Cristal Kestelman,Eduard Ayguadé Parra,Mateo Valero Cortés,Tim Harris +6 more
TL;DR: This paper introduces an advanced hardware based approach for accelerating Software Transactional Memory (STM) by proposing an implementation that is not based on the processor cache but a separate on-chip core, uses virtual addresses, does not require application modification and is further enhanced by Transactsional Memory Look-Aside Buffer.
Journal ArticleDOI
Retaining the Old Episcopal Divinity: John Edwards of Cambridge and Reformed Orthodoxy in the Later Stuart Church
TL;DR: In this article , the old Episcopal Divinity was retained by John Edwards of Cambridge and Reformed Orthodoxy in the Later Stuart Church, and the Reformation was restored to the Anglican Church.
Patent
On-demand execution of object filter code in output path of object storage service
TL;DR: In this article, the authors describe a system and methods for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests.
Posted Content
Modeling memory bandwidth patterns on NUMA machines with performance counters.
TL;DR: In this paper, the authors describe work on modeling the bandwidth requirements of an application on a NUMA compute node based on the placement of threads, and the model is parameterized by sampling performance counters during two application runs with carefully chosen thread placements.