The embodiments described herein methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory). The method includes obtaining, for each of the plurality of die, an endurance metric. The method also includes sorting the plurality of die into a plurality of die groups based on their corresponding endurance metrics, where each die group includes one or more die and each die group is associated with a range of endurance metrics. In response to a write command specifying a set of write data, the method further includes writing the write data to the non-volatile memory by writing in parallel subsets of the write data to the one or more die assigned to a single die group of the plurality of die groups.

Device and method for managing die groups

The various embodiments described herein include systems, methods and/or devices used to enable power inrush management of storage devices (e.g., DIMM devices). In one aspect, the method includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of storage device slots configured to be populated by two or more storage devices: (1) detecting a unique location associated with the storage device, (2) determining a time delay for the storage device in accordance with the unique location associated with the storage device, and (3) delaying at least one power-on operation of the storage device by the time delay for the storage device.

Power inrush management of storage devices

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Flash storage controller execute loop

The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Startup performance and power isolation

Multipass programming in buffers implemented in non-volatile data storage systems

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Timothy F. Martin

Papers

Error detection/correction based memory management