This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Closed-form equations have been developed that calculate the maximum output power and energy-conversion efficiency for an energy-harvesting circuit under power-optimized waveform excitation. The theoretical model predicts how signals with high peak-to-average power ratios increase the output power available at low input powers and decrease the maximum energy-conversion efficiency at high input powers. The model shows agreement to within 0.7 dB with ideal simulated components. Additionally, the model provides a theoretical bound for a realized microwave energy-harvesting circuit prototyped at 5.8 GHz.

Theoretical Energy-Conversion Efficiency for Energy-Harvesting Circuits Under Power-Optimized Waveform Excitation

State-of-the-art wireless sensor nodes are mostly supplied by batteries. Such systems have the disadvantage that they are not maintenance free because of the limited lifetime of batteries. Instead, wireless sensor nodes or related devices can be remotely powered. To increase the operating range and applicability of these remotely powered devices an electro-magnetic energy harvester iPs developed in a 0.13 μ m low cost CMOS technology. This paper presents an energy harvesting system that converts RF power to DC power to supply wireless sensor nodes, active transmitters or related systems with a power consumption up to the mW range. This energy harvesting system is used to power a wireless sensor node from the 900 MHz RF field. The wireless sensor node includes an on-chip temperature sensor and a bulk acoustic wave (BAW) based transmitter. The BAW resonator reduces the startup time of the transmitter to about 2 μs which reduces the amount of energy needed in one transmission cycle. The maximum output power of the transmitter is 5.4 dBm. The chip contains an ultra-low-power control unit and consumes only 190 nW in idle mode. The required input power is -19.7 dBm.

An Electro-Magnetic Energy Harvesting System With 190 nW Idle Mode Power Consumption for a BAW Based Wireless Sensor Node

Power-optimized waveforms (POWs) have been shown to increase the power-conversion efficiency in energy harvesting circuits. This paper is the first attempt to study the effects of a POW on these circuits and determine how its design can affect circuit performance. As an example, a 5.8 GHz single-shunt rectenna was designed to investigate the variation of POW parameters. It was shown that there is an optimal range of subcarrier spacing to maximize POW gain and minimize voltage ripple. Furthermore, a relationship between the maximum number of equal energy subcarriers, ripple voltage, and circuit parameters has been determined.

Rectenna performance under power-optimized waveform excitation

This paper proposes a new timing storage circuit based on memristors. Its ability to store and reproduce timing information in an analog manner without performing quantization can be useful for a wide range of applications. For continuous-time (CT) digital filters, the power and area costly analog delay blocks, which are usually implemented as inverter chains or their variants, can be replaced by the proposed timing storage circuits to delay CT digital signals in a more efficient way, especially for low-frequency biomedical applications that require very long tap delays. In addition, the same timing storage circuits also enable the storage of CT digital signals, extending the benefits of CT digital signal processing (DSP) to applications that require signal storage. As an example, a 15-tap CT finite impulse response (FIR) Savitzky-Golay (S-G) filter was designed with memristor-based delay blocks to smoothen electrocardiographic (ECG) signals accompanied with high-frequency noise. The simulated power consumption under a 3.3-volt supply was 6.63 $\mu{\rm w}$ .

A Memristor-Based Continuous-Time Digital FIR Filter for Biomedical Signal Processing

The operating range of passive UHF transponder systems is largely determined by the tag current consumption and the rectifier efficiency. Reading ranges of several meters have recently been reported for many state of the art RFID (Radio frequency IDentification) tags [1]. At this distance, the main issue for the rectifier design is the low amplitude of the high frequency antenna signal. Schottky diodes are often used for their low forward voltage drop and high switching speed. As an alternative to Schottky diodes, different circuit techniques for compensating the threshold voltage of standard transistor diodes have been utilized [4]. The transistor gates are biased near the threshold voltage, so that the devices effectively act as diodes with very low forward voltage drop. In the presented rectifier, a secondary diode charge pump is used to generate the DC bias for the threshold voltage compensation. The circuit is implemented in a standard CMOS technology and operates at a minimum available power of −11.3 dBm for an output DC power of 7.5 µW.

A UHF voltage multiplier circuit using a threshold-voltage cancellation technique

Systems which perform digital signal processing in continuous-time are attractive for a number of applications like biomedical implants, hearing aids, remote sensors, telecommunications, and audio and speech processing. A main difference to sampled data systems is the realization of the delay elements which must be implemented as quasi-continuous time delay lines. Thus a large chip area is required for the delay elements which are also a critical point of these systems. Therefore in this paper a method will be presented which allows reducing the implementation costs and power consumption of these elements. This can be achieved by granularity reduction without sacrificing performance. Furthermore implementation aspects for an integrated solution will be covered.

Optimization and implementation of continuous time DSP-systems by using granularity reduction

A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In-0.52(AlyGa1-y)(0.48)As layer with 0 < y < y(max). This barrier is lattice matched for all y to InP and is embedded between two n(+)-InGaAs layers. By varying the maximum Al-content from y(max,1) = 0.7 to y(max,2) = 1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (y(max,1) = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52 ps/V at V-D = 0.15 V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

InP-Based Unipolar Heterostructure Diode for Vertical Integration, Level Shifting, and Small Signal Rectification

We present the analog front-end for a passively powered UHF transponder with integrated temperature sensor that was designed for a 0.35 mum CMOS process with EEPROM, Schottky diodes, and double poly layers. Due to a more complex architecture and additional functionality, the power consumption of the presented sensor transponder tag is significantly larger than that of simple RFID tags. The maximum operating distance is approximately 3 m, which is less than reported values of well over 10 m for state of the art identification tags. The A/D conversion requires a stable, ripple-free supply voltage with a relatively large DC value. The aim of the front-end design in this work is to guarantee the generation and regulation of this voltage, even at a relatively high, time-varying current consumption. The design of the three main circuit blocks (the power generator, the modem, and the clock generator) is focussed on a reliable operation for different temperatures, process variations, and operating distances. All circuits have been optimized to meet these requirements while maintaining relatively low power consumption.

An Analog Front End for a Passive UHF Transponder with Temperature Sensor

The arrangement (400) has rectifier switches (402, 404) for supplying rectified voltages (Vb, Vdd) based on input alternating voltage. A transistor i.e. FET, acting as a diode has threshold voltage. A compensation circuit (406) arranged between an output of one of the switches and a control port of the transistor supplies compensation voltage to the control port such that current flow is provided between sink and source connections of the transistor with a voltage between the connections. The voltage is smaller than the threshold voltage. Independent claims are also included for the following: (1) a transponder comprising an antenna (2) a method for rectifying input alternating voltage.

Rectifier arrangement for use in transponder, has compensation circuit supplying compensation voltage to control port such that current flow is provided between sink and source connections of transistor

Tobias Feldengut

Papers

A UHF voltage multiplier circuit using a threshold-voltage cancellation technique

Optimization and implementation of continuous time DSP-systems by using granularity reduction

InP-Based Unipolar Heterostructure Diode for Vertical Integration, Level Shifting, and Small Signal Rectification

An Analog Front End for a Passive UHF Transponder with Temperature Sensor

Rectifier arrangement for use in transponder, has compensation circuit supplying compensation voltage to control port such that current flow is provided between sink and source connections of transistor