A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and method for communicating with an integrated circuit

In one aspect of the present invention, a method is provided for using a display having a predetermined display resolution to show out of focus areas in an archival image having a greater resolution than the predetermined display resolution In this method, a verification image sized for presentation on the display, is provided Portions of the archival image that are out of focus are identified The verification image is blurred so that portions of the verification image that correspond to out of focus portions of the archival image appear out of focus when the verification image is presented on the display In another aspect a camera system is provided having a source of an archival image with a predetermined resolution and a verification display having an image display resolution that is lower than the predetermined resolution of the archival image A signal processor is provided, with said signal processor processing the archival image to identify out of focus portions of the archival image and to form a verification image formatted for presentation on the verification display said signal processor further modifying the appearance of the verification image so that portions of the verification image that correlate to identified portions of the archival image appear out of focus when the modified verification image is presented on the verification display

Method and camera system for blurring portions of a verification image to show out of focus areas in a captured archival image

A digital camera includes a first image sensor, a first wide angle lens for forming a first image of a scene on the first image sensor; a second image sensor, a zoom lens for forming a second image of the same scene on the second image sensor, a control element for selecting either a first sensor output from the first image sensor or a second sensor output from the second image sensor, and a processing section for producing the output image from the selected sensor output. In one variation of this embodiment, the first lens is also a zoom lens, where the maximum focal length of the first lens is less than or equal to the minimum focal length of the second zoom lens.

Digital camera using multiple lenses and image sensors to provide an extended zoom range

There is provided an image pickup apparatus including a pixel including a photoelectric conversion element and an amplification element for amplifying and outputting a signal generated at the photoelectric conversion element, a load transistor for controlling an electric current flowing at the amplification element, and a potential control element for suppressing potential fluctuation in a first main electrode region of the load transistor which is an output side of the amplification element.

Image pickup apparatus

An image pickup apparatus is capable of suppressing a sharp variation in the state of exposure due to a variation in a field of view or a subject image, by varying the response characteristics of an exposure control device, such as an iris, a shutter or a gain, in accordance with an image magnifying rate which becomes higher as an image is electronically magnified by the operation of an electronic zoom.

Image pickup apparatus having image signal state adjusting means a response characteristic of which is controlled in accordance with image magnification rate

A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.

Testing method for electronic apparatus

A video camera including a zoom-up lens assembly magnifying an image, a charge coupled device picking up the magnified image, a recording medium for storage of the magnified image and a viewfinder having a display panel and a liquid crystal device for determining a partial area of the display panel on which the magnified image to be recorded is displayed. The liquid crystal device is controlled by a microcomputer so as to form an opaque frame-like line surrounding the partial area of the display panel.

Video camera having an improved zoom system

An integrated circuit for boundary scan is achieved to be simple structure. A testing apparatus 6 provides a testing data to a serial input port SI of a integrated circuit IC1 via a external terminal unit 2. The testing data is output to a parallel input port PI of the integrated circuit IC2 from a parallel output port SO of the integrated circuit IC1, then the testing data is output from the serial output port SO. The testing apparatus 6 compares with the testing data outputted to the integrated circuit IC1 and the testing data outputted from the integrated circuit IC2 so that a state of connection is detected between the parallel output port PO of the integrated circuit IC1 and the parallel input port PI of the integrated circuit IC2. The construction of the integrated circuits can be simplified by using both of inputting and outputting of the serial interface SIF.

Apparatus and method for testing the interconnection between integrated circuits

In order to miniaturize VCRs, various components have been integrated with semiconductor circuits, but to date video filters such as luminance LPFs, emphasis filters, and chrominance BPFs have not been integrated. We have recently developed an integrated filter circuit for processing video signals. The new circuit was fabricated using a new bipolar process called the Hiplanar process and has been applied to a dynamic emphasis IC for VCRs. Because this filter circuit operates up to 10 MHz, any video filter can be integrated by the same means.

A Fully Integrated Filter Circuit for VCRs

A fully integrated bipolar large-scale integration (LSI) signal processing system is described. The system is composed of a single-chip Y/C signal processor, a multifunction charge-coupled device (CCD) comb filter a head amplifier with active equalizers, and a PAL signal processor. About 8800 elements are integrated in the single-chip Y/C signal processor which takes the place of 5 ICs in a conventional video cassette recorder (VCR) system. The design and characteristics of the subsystems are each briefly discussed. >

Tokuya Fukuda

Papers

Testing method for electronic apparatus

Video camera having an improved zoom system

Apparatus and method for testing the interconnection between integrated circuits

A Fully Integrated Filter Circuit for VCRs

New video signal-processing LSIs for 8 mm VCRs