Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Dissection of printed edges from a fabrication layout for correcting proximity effects

An approach to reducing the size of an output file generated by an optical proximity correction (OPC) process is described. An OPC output can be examined to identify identically sized segments with identical biases. Adjoining segments to those first identified to identify repeating basic shapes. Those basic shapes can be further refined and expanded as desired. Finally, the output is rewritten making use of the repeating shapes in a hierarchical output that places each shape once as a child cell of the original geometry and uses references to that shape in other locations thereby reducing data volume size. The data volume savings can be considerable.

Method and apparatus for reducing optical proximity correction output file size

Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

Accelerated layout processing using OPC pre-processing

One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.

Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits

Techniques provided for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to the design layer.

Mask product made by selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabricat layout

The extension of optical lithography at 193nm wavelength to the 32nm node and beyond drives advanced resolution
enhancement techniques that impose even tighter tolerance requirements on wafer lithography and etch as well as on
mask manufacturing. The presence of residual errors in photomasks and the limitations of capturing those in process
models for the wafer lithography have triggered development work for separately describing and correcting mask
manufacturing effects. Long range effects - uniformity and pattern loading driven - and short range effects - proximity
and linearity - contribute to the observed signatures. The dominating source of the short range errors is the etch process
and hence it was captured with a variable etch bias model in the past [1]. The paper will discuss limitations and possible
extensions to the approach for improved accuracy. The insertion of mask process correction into a post tapeout flow
imposes strict requirements for runtime and data integrity. The paper describes a comprehensive approach for mask
process correction including calibration and model building, model verification, mask data correction and mask data
verification. Experimental data on runtime performance is presented.
Flow scenarios as well as other applications of mask process correction for gaining operational efficiency in both tapeout
and mask manufacturing are discussed.

Model based mask process correction and verification for advanced process nodes

In this paper we describe the use of sparse aerial image simulation coupled with process simulation, using the variable threshold resist (VTR) model, to do optical and process proximity correction (OPC) on phase shift masks (PSM). We will describe the OPC of PSM, including attenuated PSM, clear field PSM, and double exposure PSM. We will explain the method used to perform such OPC and show examples of critical dimension control improvements generated from such a technique. Simulations, PSM assignment and model based OPC corrections are performed with Calibre Workbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion we will show that PSM techniques need to be corrected by a phase aware proximity correction tool in order to achieve both pattern fidelity as well as small feature size on the wafer in a production environment.

Phase aware proximity correction for advanced masks

Temporal drift in the mask manufacturing process has been observed in CD measurements collected at different times.
Most of this is corrected through global sizing and dose adjustments resulting in small mean-to-target (MTT) residual
errors. However, this procedure does not account for a detectable change in the proximity behavior of the mask
process. This paper discusses a procedure for detecting and monitoring the proximity behavior of a process using an
targeted sampling plan. It also proposes a procedure to correct for drifts in proximity behavior if it is predictable and
systematic.

Application of mask process correction (MPC) to monitor and correct mask process drift

In our continued pursuit to keep up with Moor's Law we are encountering lower and lower k1
factors resulting in increased sensitivity to lithography / OPC un-friendly designs, mask rule
constraints and OPC setup file errors such as bad fragmentation, sub-optimal site placement, and
poor convergence during the OPC application process. While the process has become evermore
sensitive and more vulnerable to yield loss, the incurred costs associated with such losses is
continuing to increase in the form of higher reticle costs, longer cycle times for learning, increased
costs associated with the lithography tools, and most importantly lost revenue due to bringing a
product to market late. This has resulted in an increased need for virtual manufacturing tools that
are capable of accurately simulating the lithography process and detecting failures and weak points
in the layout so they can be resolved before committing a layout to silicon and / or identified for
inline monitoring during the wafer manufacturing process. This paper will attempt to outline a
verification flow that is employed in a high volume manufacturing environment to identify, prevent,
monitor and resolve critical lithography failures and yield inhibitors thereby minimizing how much
we succumb to the aforementioned semiconductor manufacturing vulnerabilities.

Tom Donnelly

Papers

Model based mask process correction and verification for advanced process nodes

Phase aware proximity correction for advanced masks

Application of mask process correction (MPC) to monitor and correct mask process drift

Minimizing yield-loss risks through post-OPC verification