A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Dissection of printed edges from a fabrication layout for correcting proximity effects

An approach to reducing the size of an output file generated by an optical proximity correction (OPC) process is described. An OPC output can be examined to identify identically sized segments with identical biases. Adjoining segments to those first identified to identify repeating basic shapes. Those basic shapes can be further refined and expanded as desired. Finally, the output is rewritten making use of the repeating shapes in a hierarchical output that places each shape once as a child cell of the original geometry and uses references to that shape in other locations thereby reducing data volume size. The data volume savings can be considerable.

Method and apparatus for reducing optical proximity correction output file size

Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

Accelerated layout processing using OPC pre-processing

One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.

Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits

In previous work, Cobb and Zakhor (SPIE, 2726, pp208-222, 1996) introduced the VTR (Variable Threshold Resist) model and demonstrated its accuracy for fitting empirical data for 365 nm illumination (SPIE, 3051, pp 458-468, 1997) The original work showed how EPE can be modeled as a function of a peak local image intensity and the slope of the adjacent cutline Since then, authors such as J Randall, et al, (Microel Engineering, 46, pp 59-63, 1999) have analyzed the VTR model including other parameters such as dose In the current approach, the original VTR has been enhanced to the VTR-Enhanced (or VTRE) in 1999, and VT-5 models in 2002, for production in OPC applications, which include other image intensity parameters Here we present a comprehensive report on VT (Variable Threshold) process modeling It has the demonstrated ability to accurately capture resist and etching responses, alone or in the combination with experimental VEB (Variable Etch Bias, SPIE, 4346, p 98, 2001) model, for a wide range of process conditions used in the contemporary IC manufacturing We analyzed 14 different semiconductor company processes experimental setups totaling 3000 CD measurements to prove this point We considered 248, 193, and 157 nm annular and standard illumination sources for poly, metal, and active layers We report an accuracy of VT family models under a wide range of conditions, show usage methodology, and introduce a novel method for calculating VTRE wafer predictions on a dense image intensity grid We use multiple regression method to fit VT models and discuss methods for calculating regression coefficients It is shown that models with too many eigenvectors exhibit a tendency to overfit CD curves Sub-sample cross-validation and overfitting criteria are derived to avoid this problem The section on test pattern and usage methodology describes practical issues needed for VT usage in OPC modeling Particularly we discuss the effects of metrology errors on modeling Also we introduce criteria for the important issue of model stability and propose refined test pattern structures designed to uniformly cover the VT parameter ranges It is often required that the model has to 'hit' some CD measurements exactly We introduce the 'bubble' technique to accomplish this A 'bubble' constitutes an additional term in the VT functional form; it explains single CD measurement We demonstrate how 'bubbles' help fit the pitch uniformity and iso-line linearity curves exactly Lastly, the section on dense region calculation demonstrates how this TCAD-oriented technique can be used for tuning OPC algorithms In its original form, VTR can easily be applied to sparse imaging at sample sites for OPC/ORC applications It is useful to be able to calculate the VT wafer prediction for a fully dense grid of values, and plot the results like an aerial image contour plot

Universal process modeling with VTRE for OPC

Lithography models for leading-edge OPC and design verification must be calibrated with empirical data, and this data is traditionally collected as a one-dimensional quantification of the features acquired by a CD-SEM. Two-dimensional proximity features such as line-end, bar-to-bar, or bar-to-line are only partially characterized because of the difficulty in transferring the complete information of a SEM image into the OPC model building process. A new method of two-dimensional measurement uses the contouring of large numbers of SEM images acquired within the context of a design based metrology system to drive improvement in the quality of the final calibrated model.
Hitachi High-Technologies has continued to develop "full automated EPE measurement and contouring function" based on design layout and detected edges of SEM image. This function can measure edge placement error everywhere in a SEM image and pass the result as a design layout (GDSII) into Mentor Graphics model calibration flow. Classification of the critical design elements using tagging scripts is used to weight the critical contours in the evaluation of model fitness.
During process of placement of the detected SEM edges of into the coordinate system of the design, coordinate errors inevitably are introduced because of pattern matching errors. Also, line edge roughness in 2D features introduces noise that is large compared to the model building accuracy requirements of advanced technology nodes. This required the development of contour averaging algorithms. Contours from multiple SEM images are acquired of a feature and averaged before passing into the model calibration. This function has been incorporated into the prototype Calibre Workbench model calibration flow.
Based on these methods, experimental data is presented detailing the model accuracy of a 45nm immersion lithography process using traditional 1D calibration only, and a hybrid model calibration using SEM image contours and 1D measurement results. Error sources in the contouring are assessed and reported on including systematic and random variation in the contouring results.

SEM image contouring for OPC model calibration and verification

In this paper we describe the use of sparse aerial image simulation coupled with process simulation, using the variable threshold resist (VTR) model, to do optical and process proximity correction (OPC) on phase shift masks (PSM). We will describe the OPC of PSM, including attenuated PSM, clear field PSM, and double exposure PSM. We will explain the method used to perform such OPC and show examples of critical dimension control improvements generated from such a technique. Simulations, PSM assignment and model based OPC corrections are performed with Calibre Workbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion we will show that PSM techniques need to be corrected by a phase aware proximity correction tool in order to achieve both pattern fidelity as well as small feature size on the wafer in a production environment.

Phase aware proximity correction for advanced masks

We developed a new contouring technology that executes contour re-alignment based on a matching of the measured
contour with the design data. By this 'secondary' pattern matching (the 'primary' being the pattern recognitions that is
done by the SEM during the measurement itself), rotation errors and XY shifts are eliminated, placing the measured
contour at the correct position in the design coordinates system. In the next phase, the developed method can generate
an averaged contour from multiple SEM images of identical structures, or from plural contours that are aligned
accurately by the algorithm we developed.
When the developed contouring technology is compared with the conventional one, it minimizes contouring errors and
pattern roughness effects to the minimum and enables contouring that represents the contour across the wafer.
The Contour that represents the contour across the wafer we call "Measurement Based Averaged Contour" or MBAC.
We will show that an OPC model that is built from these MBACs is more robust than an OPC model built from
contours that did not get this additional re-alignment.

High-precision contouring from SEM image in 32-nm lithography and beyond

Conventional site-base model calibration approaches have worked fine from the 180nm down to the 65nm technology nodes, but with the first 45nm technology nodes rapidly approaching, site-based model calibration techniques may not capture the details contained in these 2D-intensive designs. Due to the compaction of designs, we have slowly progressed from 1D-intensive gates, which were site-based friendly, to very complex and sometimes ornate 2D-gate regions. To compound the problem, these 2D-intensive gate regions are difficult to measure resulting in metrology-induced error when attempting to add these regions to the model calibration data. To achieve the sub-nanometer model accuracy required at this node, a model calibration technique must be able to capture the curvature induced by the process and the design in these gate regions. A new approach in model calibration had been developed in which images from a scanning electron microscope (SEM) are used together with the conventional site-base to calibrate models instead of the traditional single critical dimension (CD) approach. The advantage with the SEM-image model calibration technique is that every pixel in the SEM image contributes as CD information improving model robustness. Now the ornate gate regions could be utilized as calibration features allowing the acquisition of fine curvature in the design. 
This paper documents the issues of the site-base model calibration technique at the 45nm technology node and beyond. It also demonstrates the improvement in model accuracy for critical gate regions over the traditional modeling technique, and it shows the best know methods to achieve the utmost accuracy. Lastly, this paper shows how SEM-based modeling quantifies modeling error in these complex 2D regions.

Thuy Do

Papers

Universal process modeling with VTRE for OPC

SEM image contouring for OPC model calibration and verification

Phase aware proximity correction for advanced masks

High-precision contouring from SEM image in 32-nm lithography and beyond

Intensive 2D SEM model calibration for 45nm and beyond