International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs. In addition, it provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set. These research problems include the design of optimized test access infrastructures and test schedules.

A set of benchmarks for modular testing of SOCs

Today's computers must perform with increasing reliability, which in turn depends on the problem of determining whether a circuit has been manufactured properly or behaves correctly. However, the greater circuit density of VLSI circuits and systems has made testing more difficult and costly. This book notes that one solution is to develop faster and more efficient algorithms to generate test patterns or use design techniques to enhance testability - that is, "design for testability." Design for testability techniques offer one approach toward alleviating this situation by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is decreasing as the cost of testing rises, there is now a growing interest in these techniques for VLSI circuits.The first half of the book focuses on the problem of testing: test generation, fault simulation, and complexity of testing. The second half takes up the problem of design for testability: design techniques to minimize test application and/or test generation cost, scan design for sequential logic circuits, compact testing, built-in testing, and various design techniques for testable systems.Hideo Fujiwara is an associate professor in the Department of Electronics and Communication, Meiji University. Logic Testing and Design for Testability is included in the Computer Systems Series, edited by Herb Schwetman.

Logic testing and design for testability

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems

We propose a new scan tree architecture for test application time reduction. This technique is based on a dynamic reconfiguration mode allowing one to reduce the dependence between the test set and the final scan tree architecture. The proposed method includes two different configuration modes: the scan tree mode and the single scan mode. The proposed method does not require any additional input or output. Experimental results show up to 95% of test application time saving and test data volume reduction in comparison with a single scan chain architecture.

An efficient scan tree design for test time reduction

This paper proposes a secure scan design method whichprotects the circuits containing secret information such ascryptographic circuits from scan-based side channel attacks.The proposed method prevents the leakage of secretinformation by partial scan design based on a balancedstructure. We also guarantee the testability of both the designunder test and DFT circuitry, and therefore, realizeboth security and testability. Experiments for RSA circuitshows the effectiveness of the proposed method.

Partial Scan Approach for Secret Information Protection

This paper presents a novel circuit failure prediction mechanism for high field reliability. On-line testing at a power-on/off time of a system detects the circuits' delay degradation that is caused by aging. Dedicated test vectors are applied using BIST architecture. Embedded ring oscillators are utilized to compensate the measured delay values for temperature or voltage shift. The concept and necessary conditions for the mechanism are introduced and some preliminary experimental results show the possible effectiveness of the approach.

A circuit failure prediction mechanism (DART) for high field reliability

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results showed that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also showed that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.

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A memory grouping method for sharing memory BIST logic

This paper presents a reconfigurable union wrapper that can wrap multiple cores into a single wrapper design. Moreover, we present a test scheduling algorithm to minimize a test application time using the proposed reconfigurable union wrapper. The proposed heuristic algorithm can achieve short test application time with low computational cost compared to the conventional approaches where every core has its own wrapper. Experimental results for the ITC'02 SOC Benchmarks show the effectiveness of our approach.

Tomokazu Yoneda

Papers

An efficient scan tree design for test time reduction

Partial Scan Approach for Secret Information Protection

A circuit failure prediction mechanism (DART) for high field reliability

A memory grouping method for sharing memory BIST logic

Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers